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參數資料
| 型號： | AD7654AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數： | 15/24頁 |
| 文件大小： | 734K |
| 代理商： | AD7654AST |
REV. 0
AD7654
–15–
SAMPLING RATE – kSPS
0.1
1
10
P
100
1000
1
10
100
1000
NORMAL
IMPULSE
Figure 7. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 8 shows the detailed timing diagrams of the conversion
process. The AD7654 is controlled by the signal
CNVST
, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST
signal operates independently of
the
CS
and
RD
signals. The A0 signal is the MUX select sig-
nal that chooses which input signal will be sampled. When
high, INx1 is chosen and when low, INx2 is chosen, where x is
either A or B. It should be noted that this signal should not be
changed during the acquisition phase of the converter.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT A
ACQUIRE
CONVERT
CONVERT B
EOC
t
12
A0
t
14
t
15
t
13
t
11
t
10
Figure 8. Conversion Control
In Impulse mode, conversions can be automatically initiated. If
CNVST
is held low when BUSY is low, the AD7654 controls
the acquisition phase and automatically initiates a new con-
version. By keeping
CNVST
low, the AD7654 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up,
CNVST
should be brought low once to initiate the
conversion process. In this mode, the AD7654 could sometimes
run slightly faster than the guaranteed limits in the Impulse
mode of 444 kSPS. This feature does not exist in Normal mode.
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges and levels, and with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the
CNVST
signal
should have very low jitter. Some solutions to achieve this are to
use a dedicated oscillator for
CNVST
generation or, at least, to
clock it with a high frequency low jitter clock, as shown in Figure 5.
t
9
RESET
DATA BUS
BUSY
CNVST
t
8
Figure 9. Reset Timing
DIGITAL INTERFACE
The AD7654 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7654 digital interface accommodates either 3 V or 5 V logic
by simply connecting the OVDD supply pin of the AD7654 to the
host system interface digital supply.
Signals
CS
and
RD
control the interface. When at least one of
these signals is high, the interface outputs are in high impedance.
Usually,
CS
allows the selection of each AD7654 in multicircuit
applications and is held low in a single AD7654 design.
RD
is
generally used to enable the conversion result on the data bus.
In parallel mode, signal A/
B
allows the choice of reading either
the output of channel A or channel B, whereas in serial mode,
signal A/
B
controls which channel is output first.
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| AD7654ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7654ASTZ | 功能描述:IC ADC 16BIT 500KSPS DUAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7654ASTZ | 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LQFP48 |
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| AD7655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
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