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參數資料
| 型號： | AD7706EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance Switched Capacitor Universal Filter; Package: PDIP; No of Pins: 14; Temperature Range: 0°C to +70°C |
| 中文描述： | 3伏/ 5伏1毫瓦2-/3-Channel 16位Σ-Δ模數轉換器（264.12十一） |
| 文件頁數： | 13/32頁 |
| 文件大小： | 264K |
| 代理商： | AD7706EB |
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AD7705/AD7706
–13–
REV. A
Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 05Hex
The Clock Register is an 8-bit register from which data can either be read or to which data can be written. Table XI outlines the bit
designations for the Clock Register.
Table XI. Clock Register
ZERO (0)
ZERO (0)
ZERO (0)
CLKDIS (0)
CLKDIV (0)
CLK (1)
FS1 (0)
FS0 (1)
ZERO
Zero. A zero MUST be written to these bits to ensure correct operation of the AD7705/AD7706. Failure to do so
may result in unspecified operation of the device.
Master Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin.
When disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK
OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature.
When using an external master clock on the MCLK IN pin, the AD7705/AD7706 continues to have internal
clocks and will convert normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator
across the MCLK IN and MCLK OUT pins, the AD7705/AD7706 clock is stopped and no conversions take place
when the CLKDIS bit is active.
Clock Divider Bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two
before being used internally by the AD7705/AD7706. For example, when this bit is set to 1, the user can operate
with a 4.9152 MHz crystal between MCLK IN and MCLK OUT and internally the part will operate with the
specified 2.4576 MHz. With this bit at a Logic 0, the clock frequency appearing at the MCLK IN pin is the fre-
quency used internally by the part.
Clock Bit. This bit should be set in accordance with the operating frequency of the AD7705/AD7706. If the device
has a master clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should
be set to a “1.” If the device has a master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1),
this bit should be set to a “0.” This bit sets up the appropriate scaling currents for a given operating frequency and
also chooses (along with FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the
master clock frequency of the device, then the AD7705/AD7706 may not operate to specification.
Filter Selection Bits. Along with the CLK bit, FS1 and FS0 determine the output update rate, filter first notch and
–3 dB frequency as outlined in Table XII. The on-chip digital filter provides a sinc
3
(or Sinx/x
3
) filter response. In
association with the gain selection, it also determines the output noise of the device. Changing the filter notch
frequency, as well as the selected gain, impacts resolution. Tables I to IV show the effect of filter notch frequency
and gain on the output noise and effective resolution of the part. The output data rate (or effective conversion
time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch
of the filter is selected at 50 Hz, a new word is available at a 50 Hz output rate or every 20 ms. If the first notch is
at 500 Hz, a new word is available every 2 ms. A calibration should be initiated when any of these bits are changed.
The settling time of the filter to a full-scale step input is worst case 4
×
1/(output data rate). For example, with the
filter first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms max. If the first notch is at
500 Hz, the settling time is 8 ms max. This settling time can be reduced to 3
×
1/(output data rate) by synchroniz-
ing the step input change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit
high, the settling-time will be 3
×
1/(output data rate) from when the FSYNC bit returns low.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –
3
dB frequency =
0.262
×
filter first notch frequency
CLKDIS
CLKDIV
CLK
FS1, FS0
Table XII. Output Update Rates
CLK*
FS1
FS0
Output Update Rate
–3 dB Filter Cutoff
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20 Hz
25 Hz
100 Hz
200 Hz
50 Hz
60 Hz
250 Hz
500 Hz
5.24 Hz
6.55 Hz
26.2 Hz
52.4 Hz
13.1 Hz
15.7 Hz
65.5 Hz
131 Hz
*Assumes correct clock frequency on MCLK IN pin with CLKDIV bit set appropriately.
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