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參數資料
| 型號： | AD7707EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V 610 V Input Range 1 mW 3-Channel 16-Bit Sigma-Delta ADC(316.51 k) |
| 中文描述： | 3伏/ 5伏610 V輸入范圍1毫瓦3通道16位Σ-Δ模數轉換器（316.51十一） |
| 文件頁數： | 38/40頁 |
| 文件大小： | 316K |
| 代理商： | AD7707EB |
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REV. A
AD7707
–38–
APPENDIX 1. OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 (5 V OPERATION)
Specified high level input voltage ranges of
±
10 V,
±
5 V, 0 V to +10 V and 0 V to +5 V only utilize two gain different gain
settings (gains of 2 and 4) out of the eight possible settings available within the PGA. The tables here show what the high
level channel performance actually is over the complete range of gain settings. Table XXII shows the AD7707 output rms
noise and peak-to-peak resolution for the selectable notch and –3dB frequencies for the part, as selected by FS0, FS1 and
FS2 of the Clock Register. The numbers are given for all input ranges with a V
REF
of +2.5 V, HBIAS = 2.5 V, HICOM =
AGND and AV
DD
= 5 V. These numbers are typical and are generated at an analog input voltage of 0 V for buffered mode of
operation. Table XXIII meanwhile shows the rms and peak-to-peak resolution for buffered mode of operation.
It is important
to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but
on peak-to-peak noise.
The output noise comes from two sources. The first is the electrical noise in the semiconductor devices
(device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital
domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization
noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The
numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same
as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1
bit of resolution.
Table XXII. AIN3, Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
Unbuffered Mode
Filter First
Notch and O/P
Data Rate
Typical Output RMS Noise in
m
V (Peak-to-Peak Resolution)
Gain of
Gain of
Gain of
2
4
8
–3dB
Frequency 1
Gain of
Gain of
16
Gain of
32
Gain of
64
Gain of
128
MCLK IN = 2.4576 MHz
10Hz
50Hz
60Hz
250Hz
500Hz
2.62Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
10.90 (16)
31.34 (16)
36.74 (16)
690 (13)
4679 (10)
5.10 (16)
15.82 (16)
20.36 (16)
430 (13)
2350 (10)
3.52 (16)
9.77 (16)
12.29 (16)
212 (13)
1287 (10)
2.62 (16)
6.00 (16)
7.33 (16)
100 (13)
564 (10)
2.34 (16)
5.12 (16)
5.84 (16)
42 (13)
294 (10)
2.34 (16)
5.36 (15)
5.65 (15)
30 (13)
137 (10)
2.34 (15)
4.84 (14)
5.1 (14)
18.5 (12)
73 (10)
2.30 (14)
4.75 (13)
5.3 (13)
13.8 (12)
53 (10)
Table XXIII. AIN3, Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
Buffered Mode
Filter First
Notch and O/P
Data Rate
MCLK IN = 2.4576 MHz
10Hz
50Hz
60Hz
250Hz
500Hz
Typical Output RMS Noise in
m
V
(Peak-to-Peak Resolution)
Gain of
Gain of
Gain of
2
4
8
–3dB
Frequency 1
Gain of
Gain of
16
Gain of
32
Gain of
64
Gain of
128
2.62Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
14.28 (16)
37.4 (16)
48.8 (16)
778 (12.5)
4716 (10.5) 2423 (10.5) 1097 (10.5) 551 (10.5) 288 (10.5)
7.4 (16)
22.2 (16)
26.6 (16)
475 (13)
5.2 (16)
14.3 (16)
15.88 (16)
187 (13)
3.35 (16)
8.7 (16)
10.17 (16) 8.78 (15.5) 8.1 (14.5)
98 (13)
60 (12.5)
3.35 (16)
7.33 (15.5) 7.7 (14.5)
3.34 (15.5) 3.34 (15) 2.34 (14.5)
7.6 (13.5) 7.5 (12.5)
8.1 (13.5) 8.1 (12.5)
31.7 (12.5) 23 (12)
150 (10)
81 (10)
18.3 (11.5)
49 (10)
Output Noise For High Level Input Channel, AIN3 (3 V Operation)
Table XXIV shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and –3dB frequen-
cies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers are given for all input ranges with a
V
REF
of +1.25 V, HBIAS = 1.25 V, HICOM = AGND and AV
DD
= 3 V. These numbers are typical and are generated at an
analog input voltage of 0 V for unbuffered mode of operation. Table XXV meanwhile shows the output
rms noise and peak-to-
peak resolution
for buffered mode of operation with the same operating conditions as above.
It is important to note that these
numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak
noise. The
output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise)
used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quanti-
zation noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an
even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables
are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range
but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
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