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參數資料
| 型號： | AD7714* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V. CMOS. 500 uA Signal Conditioning ADC |
| 中文描述： | 3 V / 5號五的CMOS。 500微安ADC的信號調理 |
| 文件頁數： | 24/40頁 |
| 文件大小： | 306K |
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AD7714
REV. C
–24–
The part also offers ZS Self-Calibration and FS Self-Calibration
options. In these cases, the part performs just a zero-scale or
full-scale calibration respectively and not a full calibration of the
part. A full-scale calibration should not be carried out unless
the part contains valid zero-scale coefficients. These calibrations
are initiated on the AD7714 by writing the appropriate values
(1, 1, 0 for ZS Self-Calibration and 1, 1, 1 for FS Self Calibra-
tion) to the MD2, MD1 and MD0 bits of the Mode Register.
The zero-scale or full-scale calibration is exactly the same as
that described for the full self-calibration. In these cases, the
duration of the calibration is 3
×
1/Output Rate. At this time the
MD2, MD1 and MD0 bits in the Mode Register return to
0, 0, 0. This gives the earliest indication that the calibration
sequence is complete. The
DRDY
line goes high when calibra-
tion is initiated and does not return low until there is a valid
new word in the data register. The time from the calibration
command being issued to
DRDY
going low is 6
×
1/Output
Rate. This is made up of 3
×
1/Output Rate for the zero-scale or
full-scale calibration and 3
×
1/Output Rate for a conversion on
the analog input. If
DRDY
is low before (or goes low during)
the calibration command write to the Mode Register, it may
take up to one modulator cycle (MCLKIN/128) before
DRDY
goes high to indicate that calibration is in progress. Therefore,
DRDY
should be ignored for up to one modulator cycle after
the last bit of the calibration command is written to the Mode
Register.
The fact that the self-calibration can be performed as a two step
calibration offers another feature. After the sequence of a full
self calibration has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the part’s
zero point or gain. Calibrating one of the parameters, either
offset or gain, will not affect the other parameter.
System Calibration
System calibration allows the AD7714 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self-
calibration but uses voltage values presented by the system to
the AIN inputs for the zero- and full-scale points. Full System
calibration requires a two-step process, a ZS System Calibration
followed by a FS System Calibration.
For a full system calibration, the zero-scale point must be pre-
sented to the converter first. It must be applied to the converter
before the calibration step is initiated and remain stable until the
step is complete. Once the system zero scale has been set up at
the analog input, a ZS System Calibration is then initiated by
writing the appropriate values (0, 1, 0) to the MD2, MD1 and
MD0 bits of the Mode Register. The zero-scale system calibra-
tion is performed at the selected gain. The duration of the cali-
bration is 3
×
1/Output Rate. At this time, the MD2, MD1 and
MD0 bits in the Mode Register return to 0, 0, 0. This gives the
earliest indication that the calibration sequence is complete. The
DRDY
line goes high when calibration is initiated and does not
return low until there is a valid new word in the data register.
The time from the calibration command being issued to
DRDY
going low is 4
×
1/Output Rate. This is made up of 3
×
1/Output
Rate for the zero-scale system calibration and 1/Output Rate for
a conversion on the analog input. This conversion on the analog
input is on the same voltage as the zero-scale system calibration
and, therefore, the resultant word in the data register from this
conversion should be a zero-scale reading. If
DRDY
is low
before (or goes low during) the calibration command write to
the Mode Register, it may take up to one modulator cycle
(MCLKIN/128) before
DRDY
goes high to indicate that cali-
bration is in progress. Therefore,
DRDY
should be ignored for
up to one modulator cycle after the last bit of the calibration
command is written to the Mode Register.
After the zero-scale point is calibrated, the full-scale point is
applied to AIN and the second step of the calibration process is
initiated by again writing the appropriate values (0, 1, 1) to
MD2, MD1 and MD0. Again the full-scale voltage must be set
up before the calibration is initiated, and it must remain stable
throughout the calibration step. The full-scale system calibra-
tion is performed at the selected gain. The duration of the cali-
bration is 3
×
1/Output Rate. At this time, the MD2, MD1 and
MD0 bits in the Mode Register return to 0, 0, 0. This gives the
earliest indication that the calibration sequence is complete. The
DRDY
line goes high when calibration is initiated and does not
return low until there is a valid new word in the data register.
The time from the calibration command being issued to
DRDY
going low is 4
×
1/Output Rate. This is made up of 3
×
1/Out-
put Rate for the full-scale system calibration and 1/Output Rate
for a conversion on the analog input. This conversion on the
analog input is on the same voltage as the full-scale system
calibration and, therefore, the resultant word in the data register
from this conversion should be a full-scale reading. If
DRDY
is
low before (or goes low during) the calibration command write
to the Mode Register, it may take up to one modulator cycle
(MCLKIN/128) before
DRDY
goes high to indicate that cali-
bration is in progress. Therefore,
DRDY
should be ignored for
up to one modulator cycle after the last bit of the calibration
command is written to the Mode Register.
In the unipolar mode, the system calibration is performed
between the two endpoints of the transfer function; in the bipo-
lar mode, it is performed between midscale (zero differential
voltage) and positive full scale.
The fact that the system calibration is a two step calibration
offers another feature. After the sequence of a full system cali-
bration has been completed, additional offset or gain calibra-
tions can be performed by themselves to adjust the system zero
reference point or the system gain. Calibrating one of the
parameters, either system offset or system gain, will not affect
the other parameter. A full-scale calibration should not be car-
ried out unless the part contains valid zero-scale coefficients.
System calibration can also be used to remove any errors from
source impedances on the analog input when the part is used in
unbuffered mode. A simple R, C antialiasing filter on the front
end may introduce a gain error on the analog input voltage but
the system calibration can be used to remove this error.
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相關代理商/技術參數 |
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| AD7714ACHIPS-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
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