- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373914 > AD7714* (Analog Devices, Inc.) 3 V/5 V. CMOS. 500 uA Signal Conditioning ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7714* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V. CMOS. 500 uA Signal Conditioning ADC |
| 中文描述： | 3 V / 5號(hào)五的CMOS。 500微安ADC的信號(hào)調(diào)理 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 306K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
2
AD7714
REV. C
–9–
PIN FUNCTION DESCRIPTION
DIP/SOIC PIN NUMBERS
Pin
No. Mnemonic
Function
1
SCLK
Serial Clock. Logic Input. An external serial clock is applied to this input to access serial data from the
AD7714. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses.
Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7714 in smaller
batches of data.
Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can
be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with clock
input frequencies of both 1 MHz and 2.4576 MHz.
MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK
IN and MCLKOUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock
signal. This clock can be used to provide a clock source for external circuits.
POL
Clock Polarity. Logic Input. With this input low, the first transition of the serial clock in a data transfer
operation is from a low to a high. In microcontroller applications, this means that the serial clock should idle
low between data transfers. With this input high, the first transition of the serial clock in a data transfer
operation is from a high to a low. In microcontroller applications, this means that the serial clock should idle
high between data transfers.
SYNC
Logic Input which allows for synchronization of the digital filters and analog modulators when using a number
of AD7714s. While
SYNC
is low, the nodes of the digital filter, the filter control logic and the calibration
control logic are reset and the analog modulator is also held in its reset state.
SYNC
does not affect the digital
interface and does not reset
DRDY
if it is low.
RESET
Logic Input. Active low input which resets the control logic, interface logic, digital filter and analog modulator
of the part to power-on status.
AIN1
Analog Input Channel 1. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the positive input of a differential analog input pair when used with AIN2 (see
Communications Register section).
AIN2
Analog Input Channel 2. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the negative input of a differential analog input pair when used with AIN1 (see
Communications Register section).
AIN3
Analog Input Channel 3. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the positive input of a differential analog input pair when used with AIN4 (see
Communications Register section).
AIN4
Analog Input Channel 4. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the negative input of a differential analog input pair when used with AIN3 (see
Communications Register section).
STANDBY
Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to
typically 5
μ
A.
AV
DD
Analog Positive Supply Voltage, A Grade Versions: +3.3V nominal (AD7714-3) or +5V nominal (AD7714-5);
Y Grade Versions: 3 V or 5 V nominal.
BUFFER
Buffer Option Select. Logic Input. With this input low, the on-chip buffer on the analog input (after the
multiplexer and before the analog modulator) is shorted out. With the buffer shorted out the current flowing in
the AV
DD
line is reduced to 270
μ
A. With this input high, the on-chip buffer is in series with the analog input
allowing the inputs to handle higher source impedances.
REF IN(–)
Reference Input. Negative input of the differential reference input to the AD7714. The REF IN(–) can lie
anywhere between AV
DD
and AGND provided REFIN(+) is greater than REF IN(–).
REF IN(+)
Reference Input. Positive input of the differential reference input to the AD7714. The reference input is
differential with the provision that REF IN(+) must be greater than REF IN(–). REF IN(+) can lie anywhere
between AV
DD
and AGND.
AIN5
Analog Input Channel 5. Programmable-gain analog input which is the positive input of a differential analog
input pair when used with AIN6 (see Communications Register section).
AIN6
Analog Input Channel 6. Reference point for AIN1 through AIN4 in pseudo-differential mode or as the
negative input of a differential input pair when used with AIN5 (see Communications Register section).
AGND
Ground reference point for analog circuitry.
2
MCLK IN
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7714ARS-3 | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ARS-5 | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-3 | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-5 | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714YN | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7714ACHIPS-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714AN-3 | 制造商:Rochester Electronics LLC 功能描述:24-BIT SIGMA DELTA A/D IC - Bulk 制造商:Analog Devices 功能描述: |
| AD7714AN5 | 制造商:ANA 功能描述:24 BIT, 1KSPS, DIP 24 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。