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參數(shù)資料
| 型號(hào)： | AD7715* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V. 450 uA 16-Bit. Sigma-Delta ADC |
| 中文描述： | 3 V / 5號(hào)五，450微安16位。 Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/31頁 |
| 文件大小： | 474K |
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AD7715
–5–
REV. C
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
(A Version)
Parameter
Unit
Conditions/Comments
f
CLKIN3, 4
400
2.5
0.4
×
t
CLK IN
0.4
×
t
CLK IN
500
×
t
CLK IN
100
kHz min
MHz max
ns min
ns min
ns nom
ns min
Master Clock Frequency: Crystal Oscillator or Externally Supplied
for Specified Performance
Master Clock Input Low Time. t
CLK IN
= 1/f
CLK IN
Master Clock Input High Time
DRDY
High Time
RESET
Pulsewidth
t
CLK IN LO
t
CLK IN HI
t
1
t
2
Read Operation
t
3
t
4
t
55
0
120
0
80
100
100
100
0
10
60
100
100
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
DRDY
to
CS
Setup Time
CS
Falling Edge to SCLK Rising Edge Setup Time
SCLK Falling Edge to Data Valid Delay
DV
DD
= +5V
DV
DD
= +3.3V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Rising Edge Hold Time
Bus Relinquish Time after SCLK Rising Edge
DV
DD
= +5V
DV
DD
= +3.3V
SCLK Falling Edge to
DRDY
High
7
t
6
t
7
t
8
t
96
t
10
Write Operation
t
11
t
12
t
13
t
14
t
15
t
16
120
30
20
100
100
0
ns min
ns min
ns min
ns min
ns min
ns min
CS
Falling Edge to SCLK Rising Edge Setup Time
Data Valid to SCLK Rising Edge Setup Time
Data Valid to SCLK Rising Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Rising Edge Hold Time
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 6 and 7.
3
CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in Standby mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
4
The AD7715 is production tested with f
CLKIN
at 2.4576MHz (1MHz for some I
DD
tests). It is guaranteed by characterization to operate at 400kHz.
5
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
6
These numbers are derived from the measured time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY
returns high after the first read from the device after an output update. The same data can be read again, if required, while
DRDY
is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
TO
OUTPUT
PIN
+1.6V
I
(800
m
A AT DV
DD
= 5V
100
m
A AT DV
DD
= 3.3V)
50pF
I
(200
m
A AT DV
DD
= 5V
100
m
A AT DV
DD
= 3.3V)
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(DV
DD
= +3V to +5.25V; AV
DD
= +3V to +5.25V; AGND = DGND = 0 V; f
CLKIN
= 2.4576MHz;
Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless otherwise noted)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7715ACHIPS-3 | 3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC |
| AD7715ACHIPS-5 | 3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC |
| AD7719BRU | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| AD7719 | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| AD7719BR | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7715_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 450 ??A 16-Bit, Sigma-Delta ADC |
| AD7715-5EB | 制造商:Analog Devices 功能描述: |
| AD7715ACHIPS-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC |
| AD7715ACHIPS-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC |
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