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參數(shù)資料
型號: AD7719BR
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC
中文描述: 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝: MS-013AE, SOIC-28
文件頁數(shù): 17/40頁
文件大?。?/td> 367K
代理商: AD7719BR
REV. 0
AD7719
–17–
Table VIII. Registers—Quick Reference Guide
Power-On/Reset
Default Value
Register Name
Type
Size
Function
Communications
MSB
Write Only
8 Bits
Not Applicable
All operations to other registers are initiated through
the Communications Register. This controls whether
subsequent operations are read or write operations
and also selects the register for that subsequent
operation.
Status Register
MSB
Read Only
8 Bits
00 Hex
Provides status information on conversions, cali-
brations, error conditions, and the validity of the
reference voltage.
Mode Register
Read/Write
8 Bits
00 Hex
Controls functions such as mode of operation, chan-
nel configuration, oscillator operation in power-down.
Main ADC (AD0CON)
Control Register
Read/Write
8 Bits
07 Hex
This register is used to enable the Main ADC and
configure the Main ADC for range, channel selection,
16-/24-bit operation, and unipolar or bipolar operation.
Aux ADC (AD1CON)
Control Register
Read/Write
8 Bits
01 Hex
This register is used to enable the aux ADC and
configure the Aux ADC for range, channel selection,
unipolar or bipolar operation, and input range.
I/O (IOCON)
Control Register
Read/Write
16 Bits
0000 Hex
This register is used to control and configure the
various excitation and burnout current source options
available on-chip along with controlling the I/O port.
Filter Register
Read/Write
8 Bits
45 Hex
This register determines the amount of averaging
performed by the sinc filter and consequently deter-
mines the data update rate of the AD7719. The filter
register determines the update rate for both the main
and aux ADCs.
LSB
WEN
R/
W
0
0
A3
A2
A1
A0
LSB
RDY0
RDY1
CAL
NOREF
ERR0
ERR1
0
LOCK
MSB
LSB
SF7
SF6
SF5
SF4
SF3
SF2
SF1
SF0
MSB
LSB
0
BUF
0
CHCON
OSCPD
MD2
MD1
MD0
MSB
PSW2
PSW1
0
BO
I2PIN
I1PIN
I2EN
I1EN
LSB
P4DIR
P3DIR
P2EN
P1EN
P4DAT
P3DAT P2DAT P1DAT
MSB
LSB
AD1EN
ACH2
ACH1
ACH0
U/
B
0
0
ARN
MSB
LSB
AD0EN
WL
CH1
CH0
U/
B
RN2
RN1
RN0
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