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參數資料
| 型號： | AD7721 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| 中文描述： | 的CMOS 16位，468.75千赫，Σ-Δ模數轉換器 |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 259K |
| 代理商： | AD7721 |
AD7721
REV. A
–11–
a linear phase response. T his is very difficult to achieve with
analog filters.
Analog filters, however, can remove noise superimposed on the
signal before it reaches the ADC. Digital filtering cannot do this
and noise peaks riding on signals, near full-scale, have the po-
tential to overload the analog modulator even though the aver-
age value of the signal is within limits.
0.0
–50.0
0.5f
CLK
–100.0
–150.0
G
0.1f
CLK
0.2f
CLK
0.3f
CLK
0.4f
CLK
FREQUENCY
0.0f
CLK
Figure 9a. 128 Tap FIR Filter Frequency Response
0.0
–50.0
–100.0
–150.0
0.0f
CLK
/32
1.0f
CLK
/32
0.8f
CLK
/32
0.6f
CLK
/32
0.4f
CLK
/32
FREQUENCY
0.2f
CLK
/32
G
Figure 9b. 83 Tap FIR Filter Frequency Response
SE RIAL INT E RFACE
T he AD7721’s serial communication port allows easy inter-
facing to industry-standard microprocessors, microcontrollers
and digital signal processors. T he AD7721 is operated in self-
clocking mode, the AD7721 providing the serial clock. T he
RFS
signal is also provided by the AD7721 by tying
RFS
to
DRDY
.
Figure 10 shows the timing diagram for reading from the
AD7721.
DRDY
goes high to indicate that a conversion has
been completed.
DRDY
remains high for one internal clock
(15 MHz) cycle and then goes low for the next 31 clock cycles.
New data is loaded into the output shift register on the rising
edge of
DRDY
. When
DRDY
goes low, the data is accessed
from the AD7721. Although the AD7721 has a 12-bit digital
output in the parallel mode, sixteen bits of data are available for
transmission in the serial mode, starting with the MSB. Serial
data is clocked out of the device on the rising edge of SCLK
and is valid on the falling edge of SCLK .
CIRCUIT DE SCRIPT ION
Sigma-Delta ADC
T he AD7721 ADC employs a sigma-delta conversion technique
that converts the analog input into a digital pulse train.
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to f
CLK
/2, the noise energy which is contained
in the band of interest is reduced (Figure 8a). T o reduce the
quantization noise further, a high order modulator is employed
to shape the noise spectrum, so that most of the noise energy is
shifted out of the band of interest (Figure 8b).
T he digital filter that follows the modulator removes the large
out of band quantization noise (Figure 8c), while converting the
digital pulse train into parallel 12 bit wide binary data or serial
16 bit wide binary data.
BAND OF
INTEREST
QUANTIZATION NOISE
f
CLK
/2
a.
BAND OF
INTEREST
NOISE
SHAPING
f
CLK
/2
b.
BAND OF
INTEREST
f
CLK
/2
DIGITAL FILTER CUTOFF FREQUENCY
WHICH EQUALS 152.8kHz (10MHz) OR
229.2kHz (15MHz)
c.
Figure 8. Sigma-Delta ADC
Digital Filter
T he digital filter that follows the modulator removes the large
out of band quantization noise, while converting the one bit
digital pulse train into 12-bit or 16-bit wide binary data. T he
digital filter also reduces the data rate from f
CLK
at the input of
the filter to f
CLK
/32 at the output of the filter. T he output data
rate is a little over twice the signal bandwidth which guarantees
that there is no loss of data in the signal band.
T he AD7721 employs 2 FIR filters in series. T he first filter is a
128 tap filter that samples the output of the modulator at f
CLK
.
T he second filter is an 83 tap half-band filter that samples the
output of the first filter at f
CLK
/16 and decimates by 2. T he
frequency response of the 2 filters is shown in Figure 9.
Digital filtering has certain advantages over analog filtering.
First, since digital filtering occurs after the A/D conversion, it
can remove noise injected during the conversion process. Ana-
log filtering cannot do this. Second, the digital filter combines
low passband ripple with a steep roll off, while also maintaining
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| AD7721AN | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7721AR | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7721SQ | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7721AN | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin PDIP W |
| AD7721ANZ | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin PDIP W |
| AD7721AR | 功能描述:IC ADC 16BIT SIGMA-DELTA 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7721AR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin SOIC W T/R |
| AD7721ARZ | 功能描述:IC ADC 16BIT SIGMA-DELTA 28SOIC RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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