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參數資料
| 型號： | AD7730L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 橋傳感器模數轉換器 |
| 文件頁數： | 17/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730L |
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AD7730/AD7730L
REV. A
–17–
Bit
Location
Bit
Mnemonic
Description
MR12
B
/U
Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is 00. . . 000 for
negative full-scale input, 10 . . . 000 for zero input, and 11 . . . 111 for positive full-scale input. A 1 in
this bit selects unipolar operation and the output coding is 00 . . . 000 for zero input and 11 . . . 111 for
positive full-scale input.
MR11
DEN
Digital Output Enable Bit. With this bit at 1, the AIN2(+)/D1 and AIN2(–)/D0 pins assume their
digital output functions and the output drivers connected to these pins are enabled. In this mode, the
user effectively has two port bits which can be programmed over the serial interface.
MR10–MR9
D1–D0
Digital Output Bits. T hese bits determine the digital outputs on the AIN2(+)/D1 and AIN2(–)/D0 pins,
respectively, when the DEN bit is a 1. For example, a 1 written to the D1 bit of the Mode Register
(with the DEN bit also a 1) will put a logic 1 on the AIN2(+)/D1 pin. T his logic 1 will remain on this
pin until a 0 is written to the D1 bit (in which case the AIN2(+)/D1 pin goes to a logic 0) or the digital
output function is disabled by writing a 0 to the DEN bit.
MR8
WL
Data Word Length Bit. T his bit determines the word length of the Data Register. A 0 in this bit selects
16-bit word length when reading from the data register (i.e.,
RDY
returns high after 16 serial clock
cycles in the read operation). A 1 in this bit selects 24-bit word length for the Data Register.
MR7
HIREF
High Reference Bit. T his bit should be set in accordance with the reference voltage which is being used
on the part. If the reference voltage is 5 V, the HIREF bit should be set to 1. If the reference voltage is
2.5 V, the HIREF bit should be set to a 0. With the HIREF bit set correctly for the appropriate applied
reference voltage, the input ranges are 0 mV to +10 mV, +20 mV, +40 mV and +80 mV for unipolar
operation and
±
10 mV,
±
20 mV,
±
40 mV and
±
80 mV for bipolar operation.
It is possible for a user with a 2.5 V reference to set the HIREF bit to a 1. In this case, the part is oper-
ating with a 2.5 V reference but assumes it has a 5 V reference. As a result, the input ranges on the part
become 0 to +5 mV, +10 mV, +20 mV and +40 mV for unipolar operation and
±
5 mV,
±
10 mV,
±
20 mV and
±
40 mV for bipolar operation. However, the output noise from the part (in nV) will re-
main unchanged so the resolution of the part (in counts) will halve.
MR6
ZERO
A zero
must
be written to this bit to ensure correct operation of the AD7730.
MR5–MR4
RN1–RN0
Input Range Bits. T hese bits determine the analog input range for the selected analog input. T he dif-
ferent input ranges are outlined in T able X II. T he table is valid for a reference voltage of 5 V with the
HIREF bit at 1, or for a reference voltage of 2.5 V with the HIREF bit at a logic 0.
T able X II. Input Range Selection
Input Range
RN1
RN0
B
/U Bit = 0
B
/U Bit = 1
0
0
1
1
0
1
0
1
–10 mV to +10 mV
–20 mV to +20 mV
–40 mV to +40 mV
–80 mV to +80 mV
0 mV to +10 mV
0 mV to +20 mV
0 mV to +40 mV
0 mV to +80 mV
Power-On/Reset Default
Note that the input range given in the above table is the range that appears at the input of the PGA
after the DAC offset value has been applied. If the DAC adjusts out no offset (DAC Register is 0010
0000), then this is also the input voltage range at the analog input pins. If, for example, the DAC sub-
tracts out 50 mV of offset and the part is being operated in bipolar mode with RN1 and RN0 at 0, 0,
the actual input voltage range at the analog input is +40 mV to +60 mV.
Master Clock Disable Bit. A 1 in the bit disables the master clock from appearing at the MCLK OUT
pin. When disabled, the MCLK OUT pin is forced low. It allows the user the flexibility of using the
MCLK OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a
power saving feature. When using an external master clock at the MCLK IN pin, the AD7730 contin-
ues to have internal clocks and will convert normally with the CLK DIS bit active. When using a crystal
oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7730 clock is
stopped and no conversions take place when the CLK DIS bit is active.
MR3
CLK DIS
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相關代理商/技術參數 |
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| AD7730LBR | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 600sps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.6KSPS 24BIT SERL 24SOIC W - Tape and Reel |
| AD7730LBR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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