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參數資料
| 型號： | AD7730L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 橋傳感器模數轉換器 |
| 文件頁數： | 4/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730L |
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AD7730/AD7730L
NOT ES
1
T emperature range: –40
°
C to +85
°
C.
1
2
Sample tested during initial release.
1
3
T he offset (or zero) numbers with CHP = 1 are typically 3
μ
V precalibration. Internal zero-scale calibration reduces this by about 1
μ
V. Offset numbers with CHP = 0 can be up to
1 mV precalibration. Internal zero-scale calibration reduces this to 2
μ
V typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the
noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than
100 ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of
the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors.
1
4
T hese numbers are generated during life testing of the part.
1
5
Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See T erminology.
1
6
Recalibration at any temperature will remove these errors.
1
7
Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
1
8
Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. T he two points used to calculate the gain
error are positive full scale and negative full scale. See T erminology.
1
9
Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.
10
No Missing Codes performance with CHP = 0 and SK IP = 1 is reduced below 24 bits for SF words lower than 180 decimal.
11
T he analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs respectively.
12
T he common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
13
T he common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.
14
T hese logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
15
V
refers to DV
for all logic outputs expect D0, D1, ACX and
ACX
where it refers to AV
. In other words, the output logic high for these four outputs is determined by AV
DD
.
16
T his number represents the total drift of the channel with a zero input and the DAC output near full scale.
17
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s.
18
T hese calibration and span limits apply provided the absolute input voltage specification is obeyed. T he offset calibration limit applies to both the unipolar zero point and the
bipolar zero point.
Specifications subject to change without notice.
–4–
REV. A
TIMNGCHARACTERISTICS
1, 2
Limit at T
MIN
to T
MAX
(B Version)
Parameter
Units
Conditions/Comments
Master Clock Range
1
5
50
50
MHz min
MHz max
ns min
ns min
For Specified Performance
t
1
t
2
Read Operation
t
3
t
4
t
54
SYNC
Pulsewidth
RESET
Pulsewidth
0
0
0
60
80
0
60
80
100
100
0
10
80
100
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
RDY
to
CS
Setup T ime
CS
Falling Edge to SCLK Active Edge Setup T ime
3
SCLK Active Edge to Data Valid Delay
3
DV
DD
= +4.75 V to +5.25 V
DV
DD
= +2.75 V to +3.3 V
CS
Falling Edge to Data Valid Delay
DV
DD
= +4.75 V to +5.25 V
DV
DD
= +2.7 V to +3.3 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Inactive Edge Hold T ime
3
Bus Relinquish T ime after SCLK Inactive Edge
3
t
5A4, 5
t
6
t
7
t
8
t
96
t
10
Write Operation
t
11
t
12
t
13
t
14
t
15
t
16
SCLK Active Edge to
RDY
High
3, 7
0
30
25
100
100
0
ns min
ns min
ns min
ns min
ns min
ns min
CS
Falling Edge to SCLK Active Edge Setup T ime
3
Data Valid to SCLK Edge Setup T ime
Data Valid to SCLK Edge Hold T ime
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Edge Hold T ime
NOT ES
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 18 and 19.
3
SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
4
T hese numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
T his specification only comes into play if
CS
goes low while SCLK is low (POL = 1) or if
CS
goes low while SCLK is high (POL = 0). It is primarily required for
interfacing to DSP machines.
6
T hese numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. T his means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
RDY
returns high after the first read from the device after an output update. T he same data can be read again, if required, while
RDY
is high, although care should
be taken that subsequent reads do not occur close to the next output update.
(AV
DD
= +4.75V to +5.25V; DV
DD
= +2.7V to +5.25 V; AGND= DGND= 0 V; f
CLK IN
= 4.9152MHz;
Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwse noted).
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