- 您現在的位置：買賣IC網 > PDF目錄373915 > AD7730L (Analog Devices, Inc.) Bridge Transducer ADC PDF資料下載
參數資料
| 型號： | AD7730L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 橋傳感器模數轉換器 |
| 文件頁數： | 7/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730L |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD7730/AD7730L
REV. A
–7–
Figure 3. Signal Processing Chain
PIN CONFIGURAT ION
PIN FUNCT ION DE SCRIPT IONS
Pin
No.
Mnemonic
Function
1
SCLK
Serial Clock. Schmitt-T riggered Logic Input. An external serial clock is applied to this input to transfer serial
data to or from the AD7730. T his serial clock can be a continuous clock with all data transmitted in a con-
tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted
to or from the AD7730 in smaller batches of data.
Master Clock signal for the device. T his can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin
can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. T he AD7730 is specified
with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of
2.4576 MHz.
2
MCLK IN
SCLK
MCLK IN
DGND
DV
DD
SYNC
V
BIAS
RDY
CS
MCLK OUT
POL
DIN
DOUT
AGND
AV
DD
ACX
AIN1(+)
STANDBY
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
8
17
9
16
10
15
11
TOP VIEW
(Not to Scale)
12
13
AD7730
RESET
REF IN(–)
REF IN(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
ACX
PGA +
SIGMA-DELTA
MODULATOR
SINC
3
FILTER
CHOP
22-TAP
FIR FILTER
FASTSTEP
FILTER
CHOP
INPUT CHOPPING
THE ANALOG INPUT TO THE PART CAN BE
CHOPPED. IN CHOPPING MODE, WITH
AC EXCITATION DISABLED, THE INPUT
CHOPPING IS INTERNALTO THE DEVICE. IN
CHOPPING MODE, WITH AC EXCITATION
ENABLED, THE CHOPPING IS ASSUMED
TO BE PERFORMED EXTERNAL TO THE PART
AND NO INTERNAL INPUT CHOPPING IS
PERFORMED. THE INPUT CHOPPING CAN
BE DISABLED, IF DESIRED.
SEE PAGE 26
ANALOG
INPUT
DIGITAL
OUTPUT
SINC
3
FILTER
THE FIRST STAGE OF THE DIGITAL FILTERING
FILTER. THE
OSKIP MODE, THE SINC
3
ONLY FILTERING PERFOR FILTER IS THE
SEE PAGE 26
BUFFER
SKIP MODE
SIN SKIP MODE, THERE IS NO SECOND
SINC
FILTER IS THE ONLY FILTERING
PERFORMED ON THE PART.
SEE PAGE 29
SKIP
OUTPUT
SCALING
22-TAP FIR FILTER
SEON THE PART IS A FIXED 22-TAP FIR
BYPASSED. WHEN FASTSTEP
DETEIS PERFORMED BY THE FILTER
UNTIL HAS FULLY SETTLED.
SEE PAGE 27
OUTPUT SCALING
THE OUTPUT WORD FROM THE DIGITAL
FILTER IS SCALED BY THE CALIBRATION
COEFFICIENTS BEFORE BEING PROVIDED
AS THE CONVERSION RESULT.
SEE PAGE 29
FASTSTEP FILTER
WHEN FASTSTEP MODE IS ENABLED
HAS BEEN DETECTED, THE SECOND
STAFASTSTEP FILTER UNTIL THE FIR
FILTER HAS FULLY SETTLED.
SEE PAGE 29
OUTPUT CHOPPING
THE OUTPUT OF THE FIRST STAGE
OF FILTERING ON THE PART CAN
BE CHOPPED. IN CHOPPING MODE,
REGARDLESS OF WHETHER AC
EXCITATION IS ENABLED OR DISABLED,
THE OUTPUT CHOPPING IS
PERFORMED. THE CHOPPING CAN
BE DISABLED, IF DESIRED.
SEE PAGE 26
PGA + SIGMA-DELTA MODULATOR
THOF THE PART IS INCORPORATED
ATHE MODULATOR PROVIDES A HIGH-
FRETO THE DIGITAL FILTER.
SEE PAGE 26
BUFFER
THE SAMPLING CAPACITOR OF THE
ISCHARGING CURRENTS FROM THE
ANALOG INPUT PINS.
SEE PAGE 24
相關PDF資料 |
PDF描述 |
|---|---|
| AD7731 | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BN | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BR | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BRU | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731EB | Precision, Zero-Drift Instrumentation Amplifier; Package: SO; No of Pins: 16; Temperature Range: 0°C to +70°C |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7730LBR | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 600sps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.6KSPS 24BIT SERL 24SOIC W - Tape and Reel |
| AD7730LBR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
發布緊急采購，3分鐘左右您將得到回復。