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參數資料
| 型號： | AD7760BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.5 MSPS, 20-Bit ADC |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數： | 20/22頁 |
| 文件大小： | 868K |
| 代理商： | AD7760BSV |
AD7760
Preliminary Technical Data
AD7760 REGISTERS
The AD7760 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter
configuration, the clock divider etc. There are also digital gain, offset and over-range threshold registers. Writing to these registers
involves writing the register address first, then a 16-bit data word. Register Addresses, details of individual bits and default values are given
here.
Rev. PrN | Page 20 of 22
Table 12. Control Register 1 (Address 0x0001, Default Value 0x001A)
MSB
LSB
DL
Filt
RD
Ovr
RD
Gain
RD
Off
RD
Stat
CAL
SYNC
FLEN3
FLEN2
FLEN1
FLEN0
BYP F3
BYP F1
DEC2
DEC1
DEC0
Bit
15
Mnemonic
DL Filt
1
Comment
Download Filter. Before downloading a user defined filter, this bit must be set. The Filter Length bits must also be set at
this time. The write operations that follow will be interpreted as the user coefficients for the FIR filter until all the
coefficients and the checksum have been written.
Read Overrange. If this bit has been set, the next read operation will output the contents of the Overrange Threshold
Register instead of a conversion result.
Read Gain. If this bit has been set, the next read operation will output the contents of the digital Gain Register.
Read Offset. If this bit has been set, the next read operation will output the contents of the digital Offset Register.
Read Status. If this bit has been set, the next read operation will output the contents of the Status Register.
Calibration. Setting this bit will initiate an internal calibration routine. This routine will take 14mS with a 20MHz ICLK.
Synchronize. Setting this bit will initiate in internal synchronisation routine. Setting this bit simultaneously on multiple
devices will synchronize all filters.
Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user defined filter is downloaded.
Bypass Filter 3. If this bit is a 0, Filter 3 (Programmable FIR) will be bypassed.
Bypass Filter 1. If this bit is a 0, Filter 1 will be bypassed. This should only occur when the user requires unfiltered
modulator data to be output.
Decimation Rate. These bits set the decimation rate of Filter 2. All zeros implies that the filter is bypassed. A value of 1
corresponds to 2x decimation, a value of 2 corresponds to 4x and so on up to the maximum value of 5, corresponding
to 32x decimation.
14
RD Ovr
1,2
13
12
11
10
9
RD Gain
1,2
RD Off
1,2
RD Stat
1,2
CAL
1
SYNC
1
8-5
4
3
FLEN3:0
BYP F3
BYP F1
2-0
DEC2:0
1
Bits 15-9 are all self clearing bits.
2
Only one of the bits 14-11 may be set in any write operation as they all determine the contents of the next read operation
Table 13. Control Register 2 (Address 0x0002, Default Value 0x009B)
MSB
LSB
0
0
0
0
0
0
0
0
0
0
CDIV1
CDIV0
PD
LPWR
1
D1PD
Bit
5-4
Mnemonic
CDIV1:0
Comment
Clock Divider Bits. These set the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV[1:0] = 00
divides the MCLK by 2, setting CDIV[1:0] = 01 divides MCLK by 4. If CDIV[1:0] = 10 then the MCLK frequency is equal to
the ICLK. CDIV[1:0] = 11 is not allowed.
Power Down. Setting this bit powers down the AD7760 reducing the power consumption to TBD μW.
Low Power. If this bit is set, the AD7760 is operating in a low power mode. The power consumption is reduced for a 6dB
reduction in noise performance.
Write a ‘1’ to this bit.
Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.
3
2
PD
LPWR
1
0
D1PD
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相關代理商/技術參數 |
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