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參數資料
| 型號： | AD7825BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 48KSPS DAS with ADC, MUX, PGA and Internal Reference 28-SSOP -40 to 85 |
| 中文描述： | 4-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁數： | 13/18頁 |
| 文件大小： | 215K |
| 代理商： | AD7825BRU |
AD7822/AD7825/AD7829
–13–
REV. A
PARALLEL INTERFACE
The parallel interface of the AD7822, AD7825, and AD7829 is
eight bits wide. Figure 22 shows a timing diagram illustrating
the operational sequence of the AD7822/AD7825/AD7829
parallel interface. The multiplexer address is latched into the
AD7822/AD7825/AD7829 on the falling edge of the
RD
input.
The on-chip track/hold goes into hold mode on the falling
edge of
CONVST
and a conversion is also initiated at this
point. When the conversion is complete, the end of conversion
line (
EOC
) pulses low to indicate that new data is available in
the output register of the AD7822, AD7825, and AD7829. The
EOC
pulse will stay logic low for a maximum time of 110 ns.
However, the
EOC
pulse can be reset high by a rising edge of
CONVST
EOC
CS
RD
DB0-DB7
A0-A2
t
1
t
4
t
5
t
6
t
7
t
8
t
3
t
9
t
10
t
11
t
12
t
13
VALID
DATA
CNEXT
t
2
Figure 22. AD7822/AD7825/AD7829 Parallel Port Timing
RD
. This
EOC
line can be used to drive an edge-triggered inter-
rupt of a microprocessor.
CS
and
RD
going low accesses the
8-bit conversion result. It is possible to tie
CS
permanently low
and use only
RD
to access the data. In systems where the part is
interfaced to a gate array or ASIC, this
EOC
pulse can be applied
to the
CS
and
RD
inputs to latch data out of the AD7822,
AD7825, and AD7829 and into the gate array or ASIC. This
means that the gate array or ASIC does not need any conver-
sion status recognition logic and it also eliminates the logic
required in the gate array or ASIC to generate the read signal
for the AD7822, AD7825, and AD7829.
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