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參數資料
| 型號： | AD7825BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 48KSPS DAS with ADC, MUX, PGA and Internal Reference 28-SSOP -40 to 85 |
| 中文描述： | 4-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁數： | 7/18頁 |
| 文件大小： | 215K |
| 代理商： | AD7825BRU |
AD7822/AD7825/AD7829
–7–
REV. A
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track and hold goes into
hold mode and holds the analog input for 120 ns. This is the
acquisition phase as shown in Figure 2, when Switch 2 is in
Position A. At the point when the track and hold returns to
its track mode, this signal is sampled by the sampling capacitor
as Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, i.e., at 220 ns, while the end
of the second flash and hence the 8-bit conversion result is
available at 330 ns. As shown in Figure 4, the track-and-hold
returns to track mode after 120 ns, and starts the next acquisi-
tion before the end of the current conversion. Figure 6 shows
the ADC transfer function.
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
OUTPUT
REGISTER
OUTPUT
DRIVERS
V
IN
REFERENCE
D7
D6
D5
D4
D3
D2
D1
D0
DECODE
LOGIC
14
15
13
1
Figure 2. ADC Acquisition Phase
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
OUTPUT
REGISTER
OUTPUT
DRIVERS
V
IN
REFERENCE
D7
D6
D5
D4
D3
D2
D1
D0
DECODE
LOGIC
14
15
13
1
Figure 3. ADC Conversion Phase
HOLD
HOLD
120ns
CONVST
EOC
CS
RD
DB0-DB7
t
2
t
1
t
3
TRACK
TRACK
DATA
Figure 4. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7822,
AD7825, and AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
conversion signal (
EOC
) idles high, the falling edge of
CONVST
initiates a conversion and at the end of conversion the falling
edge of
EOC
is used to initiate an Interrupt Service Routine
(ISR) on a microprocessor. (See Parallel interface section for
more details.) V
REF
and V
MID
are connected to voltage source
such as the AD780, while V
DD
is connected to a voltage source
that can vary from 4.5 V to 5.5 V. (See Table I in Analog Input
section.) When V
DD
is first connected, the AD7822, AD7825, and
AD7829 power up in a low current mode, i.e., power-down, with
the default logic level on the
EOC
pin on the AD7822 and
AD7825 equal to a low. Ensure the
CONVST
line is not floating
when V
DD
is applied, as this could put the AD7822/AD7825/
AD7829 into an unknown state. A rising edge on the
CONVST
pin will cause the AD7829 to fully power up while a rising edge
on the
PD
pin will cause the AD7822 and AD7825 to fully power
up. For applications where power consumption is of concern,
the automatic power-down at the end of a conversion should be
used to improve power performance. (See Power-Down Options
section of the data sheet.)
SUPPLY
+4.5V TO +5.5V
10
m
F
0.1
m
F
V
DD
V
REF
V
MID
V
IN1
1.25V TO
3.75V INPUT
V
IN2
V
IN4(8)
AGND
DB0-DB7
EOC
RD
CS
CONVST
A0
A1
A2
PD
PARALLEL
INTERFACE
m
C/
m
P
AD7822/
AD7825/
AD7829
DGND
2.5V
AD780
Figure 5. Typical Connection Diagram
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