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參數資料
| 型號： | AD7825BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 48KSPS DAS with ADC, MUX, PGA and Internal Reference 28-SSOP -40 to 85 |
| 中文描述： | 4-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁數： | 15/18頁 |
| 文件大小： | 215K |
| 代理商： | AD7825BRU |
AD7822/AD7825/AD7829
–15–
REV. A
Interfacing Multiplexer Address Inputs
Figure 26 shows a simplified interfacing scheme between the
AD7825/AD7829 and any microprocessor or microcontroller,
which facilitates easy channel selection on the ADCs. The mul-
tiplexer address is latched on the falling edge of the
RD
signal,
as outlined in the Parallel Interface section, which allows the use
of the 3 LSBs of the address bus to select the channel address.
As shown in Figure 26, only address bits A3 to A15 are address
decoded allowing A0 to A2 to be changed according to desired
channel selection without affecting chip selection.
AD7825/
AD7829
A0
A1
A2
CS
RD
DB7-DB0
A15-A3
CS
RD
DB0-DB7
A15-A3
A2-A0
ADC I/O ADDRESS
MUX ADDRESS
A/D RESULT
MUX ADDRESS
(CHANNEL SELECTION A0-A2)
LATCHED
MICROPROCESSOR READ CYCLE
ADDRESS
DECODE
S
Figure 26. AD7825/AD7829 Simplified Micro Interfacing Scheme
CONVST
RD
CS
EOC
DB7-DB0
AD7822
DSP/
LATCH/ASIC
CONVST
EOC
RD
CS
DB0-DB7
A/D RESULT
t
1
t
4
Figure 27. AD7822 Stand-Alone Operation
The AD7822, being the single channel device, does not have
any multiplexer addressing associated with it and can in fact be
controlled with just one signal, i.e., the
CONVST
signal. As
shown in Figure 27 the
RD
and
CS
pins are both tied to the
EOC
pin and the resulting signal may be used as an interrupt
request signal (IRQ) on a DSP, as a
WR
signal to memory or as
a CLK to a latch or ASIC. The timing for this interface,
as shown in Figure 27, demonstrates how with the
CONVST
signal alone, a conversion may be initiated, data is latched out
and the operating mode of the AD7822 can be selected.
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