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參數(shù)資料
| 型號(hào)： | AD7827BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 14-Bit 48KSPS DAS with ADC, MUX, PGA and Internal Reference 28-SSOP -40 to 85 |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, SERIAL ACCESS, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 185K |
| 代理商： | AD7827BN |
–3–
REV. 0
AD7827
TIMNGCHARACTERISTICS
1, 2
(V
REFIN/REFOUT
= 2.5 V, all specifications –40
8
C to +105
8
C, unless otherwse noted)
Parameter
5 V
6
10%
3 V
6
10%
Units
Conditions/Comments
t
CONVERT
t
1
t
2
420
20
t
CONVERT
+t
3
t
CONVERT
+t
3
+t
7
+t
8
14
14
20
14
25
25
20
35
20
420
20
t
CONVERT
+t
3
t
CONVERT
+t
3
+t
7
+t
8
18
18
20
18
25
25
20
35
20
ns max
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
Conversion T ime.
Minimum
CONVST
Pulsewidth.
Falling edge of
CONVST
to falling edge of RFS.
t
33
t
4
t
53
t
63
t
7
t
8
t
94
Rising edge of SCLK to falling edge of RFS.
Rising edge of SCLK to rising edge of RFS.
Rising edge of SCLK to high impedance disabled.
Rising edge of SCLK to D
OUT
valid delay.
Minimum high SCLK pulse duration.
Minimum low SCLK pulse duration.
Bus relinquish time after SCLK falling edge.
t
10
Maximum delay from falling edge
CONVST
to rising edge RFS if
RFS reset by
CONVST
.
Minimum time between end of serial read and next falling edge of
CONVST
.
Power-up time from rising edge of
CONVST
using external 2.5 V
reference.
Power-up time from rising edge of
CONVST
using on-chip reference.
t
11
30
30
ns min
t
POWER-UP
1
1
μ
s max
t
POWER-UP
25
25
μ
s max
NOT ES
1
Sample tested to ensure compliance.
2
See Figures 13, 14 and 15.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V
DD
= 5 V
±
10% and time required for an
output to cross 0.4 V or 2.0 V with V
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t
9
, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
C
L
50pF
TO
OUTPUT
PIN
I
OL
I
OH
200
m
A
200
m
A
+2.1V
Figure 1. Load Circuit for Digital Output Timing Specifications
Parameter
Version B
Units
T est Conditions/Comments
POWER SUPPLY
V
DD
4.5
5.5
2.7
3.3
V min
V max
V min
V max
5 V
±
10% For Specified Performance
3 V
±
10% For Specified Performance
I
DD
Normal Operation
Power-Down
Power Dissipation
Normal Operation
Power-Down
200 kSPS
1 MSPS
10
1
mA max
μ
A max
8 mA T ypically
Logic Inputs = 0 V or V
DD
V
DD
= 3 V
T ypically 24 mW
30
mW max
9.58
47.88
mW max
mW max
NOT ES
1
See T erminology section of this data sheet.
2
Refer to the Analog Input section for an explanation of the Analog Input(s).
Specifications subject to change without notice.
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