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參數(shù)資料
| 型號(hào)： | AD7827BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 48KSPS DAS with ADC, MUX, PGA and Internal Reference 28-SSOP -40 to 85 |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, SERIAL ACCESS, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 185K |
| 代理商： | AD7827BN |
AD7827
–9–
REV. 0
OPE RAT ING MODE S
T he AD7827 has two possible modes of operation depending on
the state of the
CONVST
pulse at the end of a conversion.
Mode 1 Operation (High Speed Sampling)
When the AD7827 is operated in Mode 1 the device is not
powered down between conversions. T his mode of operation
allows high throughput rates to be achieved. Figure 13 shows
how this optimum throughput rate is achieved by bringing
CONVST
high before the end of the conversion. When operat-
ing in this mode, a new conversion should not be initiated until
30 ns after the end of a read operation. T his is to allow the
track/hold to acquire the analog signal to 0.5 LSB accuracy.
Mode 2 Operation (Automatic Power-Down)
When the AD7827 is operated in Mode 2 (see Figure 14) it
automatically powers down 530 ns after the falling edge of
CONVST
. T he
CONVST
signal is brought low to initiate a
conversion and is left logic low until 530 ns has elapsed after the
falling edge of the
CONVST
pulse, i.e., before Point A or Point
B in Figure 14, depending on the actual value of t
2
(see T iming
Characteristics). T he state of the
CONVST
signal is sampled at
this point (i.e., 530 ns after
CONVST
falling edge) and the
AD7827 will power down as long as the
CONVST
is low. T he
ADC is powered up again on the rising edge of the
CONVST
signal. T he
CONVST
pulse width does not have to be as long as
the power-up time if an external reference is used (see Power-Up
T imes section). Superior power performance can be achieved in
this mode of operation by powering up the AD7827 to only
carry out a conversion. T he serial interface of the AD7827 is
still fully operational while the device is powered down.
t
2
t
1
CURRENT CONVERSION
RESULT
CONVST
RFS
SCLK
D
OUT
Figure 13. Mode 1 Operation Timing Diagram
t
2
CURRENT CONVERSION
RESULT
CONVST
RFS
SCLK
D
OUT
t
POWER-UP
A
B
Figure 14. Mode 2 Operation Timing Diagram
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