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參數資料
| 型號： | AD7851AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MO-095AG, DIP-24 |
| 文件頁數： | 4/36頁 |
| 文件大小： | 435K |
| 代理商： | AD7851AN |
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AD7851
–4–
REV. A
Limit at T
MIN
, T
MAX
A, K
Parameter
Units
Description
f
CLK IN2
500
7
10
f
CLK IN
100
50
3.25
–0.4 t
SCLK
±
0.4 t
SCLK
0.6 t
SCLK
30
30
45
30
20
0.4 t
SCLK
0.4 t
SCLK
30
30/0.4 t
SCLK
50
50
90
50
2.5 t
CLK IN
2.5 t
CLK IN
41.7
kHz min
MHz max
MHz max
MHz max
ns min
ns max
μ
s max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
Master Clock Frequency
f
SCLK3
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST
Pulse Width
CONVST
↓
to BUSY
↑
Propagation Delay
Conversion T ime = 20 t
CLK IN
SYNC
↓
to SCLK
↓
Setup T ime (Noncontinuous SCLK Input)
SYNC
↓
to SCLK
↓
Setup T ime (Continuous SCLK Input)
SYNC
↓
to SCLK
↓
Setup T ime. Interface Mode 4 Only
Delay from
SYNC
↓
until DOUT 3-State Disabled
Delay from
SYNC
↓
until DIN 3-State Disabled
Data Access T ime After SCLK
↓
Data Setup T ime Prior to SCLK
↑
Data Valid to SCLK Hold T ime
SCLK High Pulse Width (Interface Modes 4 and 5)
SCLK Low Pulse Width (Interface Modes 4 and 5)
SCLK
↑
to
SYNC
↑
Hold T ime (Noncontinuous SCLK )
(Continuous SCLK ) Does Not Apply to Interface Mode 3
SCLK
↑
to
SYNC
↑
Hold T ime
Delay from
SYNC
↑
until DOUT 3-State Enabled
Delay from SCLK
↑
to DIN Being Configured as Output
Delay from SCLK
↑
to DIN Being Configured as Input
CAL
↑
to BUSY
↑
Delay
CONVST
↓
to BUSY
↑
Delay in Calibration Sequence
Full Self-Calibration T ime, Master Clock Dependent (250026
t
CLK IN
)
Internal DAC Plus System Full-Scale Cal T ime, Master Clock
Dependent (222228 t
CLK IN
)
System Offset Calibration T ime, Master Clock Dependent
(27798 t
CLK IN
)
Delay from CLK to SCLK
t
14
t
2
t
CONVERT
t
3
t
4
t
55
t
5A5
t
65
t
7
t
8
t
96
t
106
t
11
t
11A
t
127
t
13
t
148
t
15
t
16
t
CAL9
t
CAL19
37.04
ms typ
t
CAL29
4.63
ms typ
t
DELAY
65
ns max
NOT ES
Descriptions that refer to SCLK
↑
(rising) or SCLK
↓
(falling) edges here are with the POLARIT Y pin HIGH. For the POLARIT Y pin LOW then the opposite edge of
SCLK will apply.
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. See
T able X and timing diagrams for different interface modes and calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f
.
4
T he
CONVST
pulse width will here only apply for normal operation. When the part is in power-down mode, a different
CONVST
pulse width will apply (see Power-
Down section).
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t
7
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t
12
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
8
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time quoted in the timing characteristics is the true delay of the part in
turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
9
T he typical time specified for the calibration times is for a master clock of 6 MHz.
Specifications subject to change without notice.
= 0.5 t
.
TIMNGSPECIFICATIONS
1
(AV
DD
= DV
DD
= +5.0 V
6
5%; f
CLKIN
= 6 MHz, T
A
= T
MN
to T
MAX
, unless otherwse noted)
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