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參數資料
| 型號： | AD7854 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉換器) |
| 中文描述： | 12位采樣ADC（單電源，速度高達200ksps的12位采樣的A / D轉換器） |
| 文件頁數： | 13/28頁 |
| 文件大小： | 268K |
| 代理商： | AD7854 |
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AD7854/AD7854L
REV. 0
–13–
When using the software conversion start for maximum
throughput, the user must ensure the control register write
operation extends beyond the falling edge of BUSY. T he falling
edge of BUSY resets the
CONVST
bit to 0 and allows it to be
reprogrammed to 1 to start the next conversion.
T Y PICAL CONNE CT ION DIAGRAM
Figure 8 shows a typical connection diagram for the AD7854/
AD7854L. T he AGND and the DGND pins are connected
together at the device for good noise suppression. T he first
CONVST
applied after power-up starts a self-calibration
sequence. T his is explained in the
calibration
section of the data
sheet. Applying the
RD
and
CS
signals causes the conversion
result to be output on the 12 data pins. Note that after power is
applied to AV
DD
and DV
DD
, and the
CONVST
signal is applied,
the part requires (70 ms + 1/sample rate) for the internal refer-
ence to settle and for the self-calibration to be completed.
4MHz/1.8MHz
OSCILLATOR
AV
DD
DV
DD
AIN(+)
AIN(–)
C
REF1
C
REF2
DB11
DB0
CONVST
AGND
DGND
CLKIN
REF
IN
/REF
OUT
AD7854/
AD7854L
ANALOG
SUPPLY
+3V TO +5V
0.1μF
0.1μF
10μF
0.1μF
0.01μF
CONVERSION
START SIGNAL
0.1nF EXTERNAL REFERENCE
0.1μF ON-CHIP REFERENCE
0V TO 2.5V
INPUT
OPTIONAL
EXTERNAL
REFERENCE
CS
RD
WR
BUSY
AD780/
REF192
μC/μP
HBEN
Figure 8. Typical Circuit
For applications where power consumption is a major concern,
the power-down options can be programmed by writing to the
part. See Power-Down section for more detail on low power
applications.
CIRCUIT INFORMAT ION
T he AD7854/AD7854L is a fast, 12-bit single supply A/D con-
verter. T he part requires an external 4 MHz/1.8 MHz master
clock (CLK IN), two C
REF
capacitors, a
CONVST
signal to start
conversion and power supply decoupling capacitors. T he part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter and parallel interface logic functions on
a single chip. T he A/D converter section of the AD7854/
AD7854L consists of a conventional successive-approximation
converter based around a capacitor DAC. T he AD7854/
AD7854L accepts an analog input range of 0 to +V
REF.
V
REF
can be tied to V
DD
. T he reference input to the part connected
via a 150 k
resistor to the internal 2.5 V reference and to the
on-chip buffer.
A major advantage of the AD7854/AD7854L is that a conver-
sion can be initiated in software as well as applying a signal to
the
CONVST
pin. T he part is available in a 28-pin SSOP pack-
age, and this offers the user considerable space saving advan-
tages over alternative solutions. T he AD7854L version typically
consumes only 5.5 mW making it ideal for battery-powered
applications.
CONVE RT E R DE T AILS
T he master clock for the part is applied to the CLK IN pin.
Conversion is initiated on the AD7854/AD7854L by pulsing the
CONVST
input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of
CONVST
(or at
the end of the control register write operation), the on-chip
track/hold goes from track to hold mode. T he falling edge of the
CLK IN signal which follows the rising edge of
CONVST
ini-
tiates the conversion, provided the rising edge of
CONVST
(or
WR
when converting via the control register) occurs typically at
least 10 ns before this CLK IN edge. T he conversion takes
16.5 CLK IN periods from this CLK IN falling edge. If the
10 ns setup time is not met, the conversion takes 17.5 CLK IN
periods.
T he time required by the AD7854/AD7854L to acquire a signal
depends upon the source resistance connected to the AIN(+)
input. Please refer to the Acquisition T ime section for more
details.
When a conversion is completed, the BUSY output goes low,
and the result of the conversion can be read by accessing the
data through the data bus. T o obtain optimum performance
from the part, read or write operations should not occur during
the conversion or less than 200 ns prior to the next
CONVST
rising edge. Reading/writing during conversion typically de-
grades the Signal to (Noise + Distortion) by less than 0.5 dBs.
T he AD7854 can operate at throughput rates of over 200 kSPS
(up to 100 kSPS for the AD7854L).
With the AD7854L, 100 kSPS throughput can be obtained as
follows: the CLK IN and
CONVST
signals are arranged to give
a conversion time of 16.5 CLK IN periods as described above
and 1.5 CLK IN periods are allowed for the acquisition time.
With a 1.8 MHz clock, this gives a full cycle time of 10
μ
s,
which equates to a throughput rate of 100 kSPS.
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| AD7858LARS | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7854AD | 制造商:Analog Devices 功能描述: |
| AD7854AQ | 功能描述:IC ADC 12BIT PARALLEL LP 28-CDIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7854AR | 功能描述:IC ADC 12BIT PARALLEL LP 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7854AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Parallel 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 200KSPS 12-BIT PARALLEL 28SOIC W - Tape and Reel |
| AD7854ARS | 功能描述:IC ADC 12BIT PARALLEL LP 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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