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參數資料
| 型號： | AD7854LAQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, CERDIP-28 |
| 文件頁數： | 20/28頁 |
| 文件大小： | 264K |
| 代理商： | AD7854LAQ |
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AD7854/AD7854L
–
20
–
REV. B
CALIBRATION SECTION
Calibration Overview
The automatic calibration that is performed on power-up
ensures that the calibration options covered in this section are
not required in a significant number of applications. A calibration
does not have to be initiated unless the operating conditions
change (CLKIN frequency, analog input mode, reference volt-
age, temperature, and supply voltages). The AD7854/AD7854L
has a number of calibration features that may be required in
some applications, and there are a number of advantages in per-
forming these different types of calibration. First, the internal
errors in the ADC can be reduced significantly to give superior
dc performance; and second, system offset and gain errors can
be removed. This allows the user to remove reference errors
(whether it be internal or external reference) and to make use of
the full dynamic range of the AD7854/AD7854L by adjusting
the analog input range of the part for a specific system.
There are two main calibration modes on the AD7854/AD7854L,
self-calibration and system calibration. There are various op-
tions in both self-calibration and system calibration as outlined
previously in Table III. All the calibration functions are initi-
ated by writing to the control register and setting the STCAL
bit to 1.
The duration of each of the different types of calibration is given
in Table IX for the AD7854 with a 4 MHz master clock. These
calibration times are master clock dependent. Therefore the
calibration times for the AD7854L (CLKIN = 1.8 MHz) are
larger than those quoted in Table VIII.
Table VIII. Calibration Times (AD7854 with 4 MHz CLKIN)
Type of Self-Calibration or System Calibration
Time
Full
Gain + Offset
Offset
Gain
31.25 ms
6.94 ms
3.47 ms
3.47 ms
Automatic Calibration on Power-On
The automatic calibration on power-on is initiated by the first
CONVST
pulse after the AV
DD
and DV
DD
power on. From the
CONVST
pulse the part internally sets a 32/72 ms (4 MHz/
1.8 MHz CLKIN) timeout. This time is large enough to ensure
that the internal reference has settled before the calibration is
performed. However, if an external reference is being used, this
reference must have stabilized before the automatic calibration
is initiated. This first
CONVST
pulse also triggers the BUSY
signal high, and once the 32/72 ms has elapsed, the BUSY signal
goes low. At this point the next
CONVST
pulse that is applied
initiates the automatic full self-calibration. This
CONVST
pulse
again triggers the BUSY signal high, and after 32/72 ms (4 MHz/
1.8 MHz CLKIN), the calibration is completed and the BUSY
signal goes low. This timing arrangement is shown in Figure 28.
The times in Figure 28 assume a 4 MHz/1.8 MHz CLKIN
signal.
AV
DD
= DV
DD
CONVST
BUSY
POWER ON
32/72 ms
TIMEOUT PERIOD
AUTOMATIC
CALIBRATION
DURATION
32/72 ms
CONVERSION IS INITIATED
ON THIS EDGE
Figure 28. Timing Arrangement for Autocalibration on
Power-On
The
CONVST
signal is gated with the BUSY internally so that
as soon as the timeout is initiated by the first
CONVST
pulse all
subsequent
CONVST
pulses are ignored until the BUSY signal
goes low, 32/72 ms later. The
CONVST
pulse that follows after
the BUSY signal goes low initiates an automatic full self-
calibration. This takes a further 32/72 ms. After calibration,
the part is accurate to the 12-bit level and the specifications
quoted on the data sheet apply, and all subsequent
CONVST
pulses initiate conversions. There is no need to perform another
calibration unless the operating conditions change or unless a
system calibration is required.
This autocalibration at power-on is disabled if the user writes to
the control register before the autocalibration is initiated. If the
control register write operation occurs during the first 32/72 ms
timeout period, then the BUSY signal stays high for the 32/72 ms
and the
CONVST
pulse that follows the BUSY going low does
not initiate an automatic full self-calibration. It initiates a con-
version and all subsequent
CONVST
pulses initiate conversions
as well. If the control register write operation occurs when the
automatic full self-calibration is in progress, then the calibration
is not be aborted; the BUSY signal remains high until the auto-
matic full self-calibration is complete.
Self-Calibration Description
There are four different calibration options within the self-
calibration mode. There is a full self-calibration where the
DAC, internal offset, and internal gain errors are removed.
There is the (Gain + Offset) self-calibration which removes the
internal gain error and then the internal offset errors. The inter-
nal DAC is not calibrated here. Finally, there are the self-offset
and self-gain calibrations which remove the internal offset errors
and the internal gain errors respectively.
The internal capacitor DAC is calibrated by trimming each of
the capacitors in the DAC. It is the ratio of these capacitors to
each other that is critical, and so the calibration algorithm
ensures that this ratio is at a specific value by the end of the
calibration routine. For the offset and gain there are two
separate capacitors, one of which is trimmed during offset
calibration and one of which is trimmed during gain calibration.
In bipolar mode the midscale error is adjusted by an offset cali-
bration and the positive full-scale error is adjusted by the gain
calibration. In unipolar mode the zero-scale error is adjusted by
the offset calibration and the positive full-scale error is adjusted
by the gain calibration.
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| AD7854LAR | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854ARS | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854AQ | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854SQ | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854L* | 3.3V/5V Low Power RS232 3-Driver/5-Receiver Transceiver; Package: SSOP; No of Pins: 28; Temperature Range: 0°C to +70°C |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7854LAR | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:12-BIT SINGLE CHANNEL PARALLEL ADC I.C. - Bulk |
| AD7854LAR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 12-BIT PARALLEL 28SOIC W - Tape and Reel |
| AD7854LARS | 功能描述:IC ADC 12BIT PARALLEL LP 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD7854LARS-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SSOP T/R |
| AD7854LARSZ | 功能描述:IC ADC 12BIT PARALLEL LP 28SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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