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參數資料
| 型號： | AD7854LAQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, CERDIP-28 |
| 文件頁數： | 8/28頁 |
| 文件大小： | 264K |
| 代理商： | AD7854LAQ |
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AD7854/AD7854L
–
8
–
REV. B
AD7854/AD7854L ON-CHIP REGISTERS
The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7854/AD7854L will operate as a read-only ADC. The
WR
pin should be tied to DV
DD
for operating the AD7854/AD7854L as a
read-only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7854/AD7854L contains a
control register, ADC output data register, status register, test register
and
10 calibra-
tion registers
. The control register is write-only, the ADC output data register and the status register are read-only, and the test and
calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first
8 bits of data that are written
must
consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written
must
consist of the
8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each
transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to
determine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the
address bits, while Figure 2 shows the overall write register hierarchy.
Table I. Write Register Addressing
ADDR1
ADDR0
Comment
0
0
1
0
1
0
This combination does not address any register.
This combination addresses the
TEST REGISTER
. The 14 LSBs of data are written to the test register.
This combination addresses the
CALIBRATION REGISTER
. The 14 least significant data bits are writ-
ten to the selected calibration register.
This combination addresses the
CONTROL REGISTER
. The 14 least significant data bits are written to
the control register.
1
1
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. Note: when reading from the calibration registers, the low byte must always be read first.
Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register
until the read selection bits are changed in the control register.
Table II. Read Register Addressing
RDSLT1
RDSLT0
Comment
0
0
All successive read operations are from the
ADC OUTPUT DATA REGISTER
. This is the default power-
up setting. There is always four leading zeros when reading from the ADC output data register.
All successive read operations are from the
TEST REGISTER
.
All successive read operations are from the
CALIBRATION REGISTERS
.
All successive read operations are from the
STATUS REGISTER
.
0
1
1
1
0
1
TEST
REGISTER
CALIBRATION
REGISTERS
CONTROL
REGISTER
ADDR1, ADDR0
DECODE
01
10
11
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
OFFSET(1)
OFFSET(1)
GAIN(1)
CALSLT1, CALSLT0
DECODE
00
01
10
11
Figure 2. Write Register Hierarchy/Address Decoding
TEST
REGISTER
CALIBRATION
REGISTERS
CONTROL
REGISTER
RDSLT1, RDSLT0
DECODE
01
10
11
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
OFFSET(1)
OFFSET(1)
GAIN(1)
CALSLT1, CALSLT0
DECODE
00
01
10
11
ADC OUTPUT
DATA REGISTER
00
Figure 3. Read Register Hierarchy/Address Decoding
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| AD7854L* | 3.3V/5V Low Power RS232 3-Driver/5-Receiver Transceiver; Package: SSOP; No of Pins: 28; Temperature Range: 0°C to +70°C |
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|---|---|
| AD7854LAR | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:12-BIT SINGLE CHANNEL PARALLEL ADC I.C. - Bulk |
| AD7854LAR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 12-BIT PARALLEL 28SOIC W - Tape and Reel |
| AD7854LARS | 功能描述:IC ADC 12BIT PARALLEL LP 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD7854LARS-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin SSOP T/R |
| AD7854LARSZ | 功能描述:IC ADC 12BIT PARALLEL LP 28SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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