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參數(shù)資料
| 型號： | AD7866ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 304K |
| 代理商： | AD7866ARU |
REV. 0
AD7866
–15–
To enter Partial Power-Down, the conversion process must be
interrupted by bringing
CS
high anywhere after the second falling
edge of SCLK and before the 10th falling edge of SCLK as shown
in Figure 17. Once
CS
has been brought high in this window of
SCLKs, the part will enter Partial Power-Down and the conver-
sion that was initiated by the falling edge of
CS
will be terminated
and D
OUT
A and D
OUT
B will go back into three-state. If
CS
is
brought high before the second SCLK falling edge, the part
will remain in normal mode and will not power down. This will
avoid accidental power-down due to glitches on the
CS
line.
In order to exit this mode of operation and power the AD7866 up
again, a dummy conversion is performed. On the falling edge of
CS
the device will begin to power up, and will continue to power up as
long as
CS
is held low until after the falling edge of the 10th SCLK.
In the case of an external reference, the device will be fully pow-
ered up once 16 SCLKs have elapsed and valid data will result
from the next conversion as shown in Figure 18. If
CS
is brought
high before the second falling edge of SCLK, the AD7866 will again
go into partial power-down. This avoids accidental power-up due
to glitches on the
CS
line; although the device may begin to power
up on the falling edge of
CS
, it will power down again on the rising
edge of
CS
. If the AD7866 is already in Partial Power-Down mode
and
CS
is brought high between the second and tenth falling edges
of SCLK, the device will enter Full Power-Down mode. For more
information on the power-up times associated with partial power-
down in various configurations, see the Power-Up Times section.
Full Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required than those in the Partial Power-
Down mode, as power-up from a Full Power-Down takes sub-
stantially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions performed
at a relatively high throughput rate would be followed by a long
period of inactivity and hence power-down. When the AD7866 is
in Full Power-Down, all analog circuitry is powered down. Full
Power-Down is entered in a similar way as Partial Power-Down,
except the timing sequence shown in Figure 17 must be executed
twice. The conversion process must be interrupted in a similar
fashion by bringing
CS
high anywhere after the second falling
edge of SCLK and before the 10th falling edge of SCLK. The device
will enter Partial Power Down at this point. To reach Full Power-
Down, the next conversion cycle must be interrupted in the
same way, as shown in Figure 19. Once
CS
has been brought high
in this window of SCLKs, the part will power down completely.
NOTE: It is not necessary to complete the 16 SCLKs once
CS
has been brought high to enter a power-down mode.
To exit Full Power-Down, and power the AD7866 up again, a
dummy conversion is performed, as when powering up from
Partial Power-Down. On the falling edge of
CS
the device
will begin to power up, and will continue to power up as long as
CS
is held low until after the falling edge of the 10th SCLK.
The power-up time required must elapse before a conversion
can be initiated as shown in Figure 20. See the Power-up Times
section for the power-up times associated with the AD7866.
POWER-UP TIMES
The AD7866 has two power-down modes, Partial Power-
Down and Full Power-Down, which are described in detail in
the Modes of Operation section. This section deals with the
power-up time required when coming out either of these
modes. It should be noted that the power-up times quoted
apply with the recommended capacitors on the V
REF
, D
CAP
A,
and D
CAP
B pins in place.
To power up from Full Power-Down approximately 4 ms should
be allowed from the falling edge of
CS
, shown in Figure 20 as
t
POWER UP
. Powering up from Partial Power-Down requires
much less time. If the internal reference is being used, the power-up
CS
1
16
10
2
THREE-STATE
SCLK
D
OUT
A
D
OUT
B
Figure 17. Entering Partial Power-Down Mode
1
16
10
1
16
INVALID DATA
VALID DATA
CS
SCLK
D
OUT
A
D
OUT
B
THE PART BEGINS
TO POWER UP
THE PART MAY BE FULLY
POWERED UP; SEE POWER-UP
TIMES SECTION
A
Figure 18. Exiting Partial Power-Down Mode
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