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參數資料
| 型號： | AD7866ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數： | 17/20頁 |
| 文件大小： | 304K |
| 代理商： | AD7866ARU |
REV. 0
AD7866
–17–
POWER VERSUS THROUGHPUT RATE
By using the Partial Power-Down mode on the AD7866 when not
converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 21 shows how as the throughput
rate is reduced, the part remains in its partial power-down state longer
and the average power consumption over time drops accordingly.
THROUGHPUT
–
kSPS
0.01
0
P
–
50
100
V
= 5V
SCLK = 20MHz
150
200
250
300
350
0.1
1
10
100
V
DD
= 3V
SCLK = 20MHz
Figure 21. Power vs. Throughput for Partial Power-Down
For example, if the AD7866 is operated in a continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz
(V
DD
= 5 V), and the device is placed in Partial Power-Down mode
between conversions, then the power consumption is calculated
as follows. The maximum power dissipation during normal
operation is 24 mW (V
DD
= 5 V). If the power-up time allowed
from Partial Power-Down is one dummy cycle, i.e., 1
μ
s, (assumes
use of an external reference) and the remaining conversion time is
another cycle, i.e., 1
μ
s, then the AD7866 can be said to dissipate
24 mW for 2
μ
s during each conversion cycle. For the remainder of
the conversion cycle, 8
μ
s, the part remains in Partial Power-Down
mode. The AD7866 can be said to dissipate 2.8 mW for the
remaining 8
μ
s of the conversion cycle. If the throughput rate is
100 kSPS, the cycle time is 10
μ
s and the average power dissipated
during each cycle is (2/10)
(24 mW) + (8/10)
7.04 mW. If V
DD
= 3 V, SCLK = 20 MHz and the device is again
in Partial Power-Down mode between conversions, the power
dissipated during normal operation is 8.4 mW. The AD7866 can
be said to dissipate 8.4 mW for 2 ms during each conversion
cycle and 1.68 mW for the remaining 8 ms where the part is
in Partial Power-Down. With a throughput rate of 100 kSPS,
the average power dissipated during each conversion cycle is
(2/10)
(8.4 mW) + (8/10)
(1.68 mW) = 3.02 mW. Figure 21
shows the power versus throughput rate when using the Partial
Power-Down mode between conversions with both 5 V and 3 V
supplies for the AD7866.
(2.8 mW) =
SERIAL INTERFACE
Figure 22 shows the detailed timing diagram for serial interfacing
to the AD7866. The serial clock provides the conversion clock
and also controls the transfer of information from the AD7866
during conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode,
takes the bus out of three-state and the analog input is sampled at
this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. Once 13 SCLK falling edges
have elapsed, then the track and hold will go back into track on
the next SCLK rising edge as shown in Figure 22 at point B. On
the rising edge of
CS
, the conversion will be terminated and D
OUT
A
and D
OUT
B will go back into three-state. If
CS
is not brought
high, but instead held low for a further 16 SCLK cycles on
CS
SCLK
D
OUT
A
D
OUT
B
t
2
1
2
3
4
5
13
14
15
16
t
3
t
4
t
7
t
5
t
8
t
QUIET
0
RANGE
A0
A/B
DB11
DB2
DB1
DB0
THREE-
STATE
1 LEADING ZERO,
3 STATUS BITS
DB10
THREE-
STATE
t
6
B
Figure 22. Serial Interface Timing Diagram
CS
SCLK
D
OUT
A
t
2
t
4
t
7
t
5
0
RANGE
DB11
A
A0/
A0
ZERO
DB1
A
DB0
A
ZERO
RANGE
A0/
A0
ONE
DB11
B
DB1
B
DB0
B
THREE-
STATE
t
6
t
9
1 LEADING ZERO,
3 STATUS BITS
1 LEADING ZERO,
3 STATUS BITS
THREE-
STATE
t
3
1
2
3
4
5
14
15
16
17
32
Figure 23. Reading Data from Both ADCs on One D
OUT
Line
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