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參數資料
| 型號： | AD7868BQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | LC2MOS Complete, 12-Bit Analog I/O System |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁數： | 3/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7868BQ |
A
Version
1
B
Version
1
T
Version
1
Parameter
Units
T est Conditions/Comments
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio
(SNR) @ +25
°
C
T
to T
T otal Harmonic Distortion (T HD)
70
70
–78
72
71
–78
70
70
–76
dB min
dB min
dB max
V
= 1 kHz Sine Wave, f
= 83 kHz
T ypically 71.5 dB at +25
°
C for 0 < V
< 20 kHz
4
V
= 1 kHz Sine Wave, f
= 83 kHz
T ypically –84 dB at +25
°
C for 0 < V
< 20 kHz
4
V
= 1 kHz Sine Wave, f
= 83 kHz
T ypically –84 dB at +25
°
C for 0 < V
OUT
< 20 kHz
4
Peak Harmonic or Spurious Noise
–78
–78
–76
dB max
DC ACCURACY
Resolution
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Full-Scale Error
5
Negative Full-Scale Error
5
12
±
1/2
12
±
1/2
±
1
±
0.9
±
5
±
5
±
5
12
±
1/2
±
1
±
0.9
±
5
±
5
±
5
Bits
LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max
±
0.9
±
5
±
5
±
5
Guaranteed Monotonic
REFERENCE OUT PUT
6
RO ADC @ +25
°
C
RO ADC T C
RO ADC T C
Reference Load Change (
RO DAC vs.
I)
2.99/3.01
±
25
2.99/3.01
±
25
±
40
–1.5
2.99/3.01
±
25
±
50
–1.5
V min/V max
ppm/
°
C typ
ppm/
°
C max
mV max
–1.5
Reference Load Current Change (0–500
μ
A)
REFERENCE INPUT
RI DAC Input Range
Input Current
2.85/3.15
1
2.85/3.15
1
2.85/3.15
1
V min/V max 3 V
±
5%
μ
A max
LOGIC INPUT S (
LDAC
,
TFS
, T CLK , DT )
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
Input Capacitance, C
IN7
2.4
0.8
±
10
10
2.4
0.8
±
10
10
2.4
0.8
±
10
10
V min
V max
μ
A max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
ANALOG INPUT
Output Voltage Range
dc Output Impedance
Short-Circuit Current
±
3
0.3
20
±
3
0.3
20
±
3
0.3
20
V nom
typ
mA typ
AC CHARACT ERIST ICS
7
Voltage Output Settling-T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
Digital Feedthrough
V
IN
to V
OUT
Isolation
Settling T ime to Within
±
1/2 LSB of Final Value
T ypically 2
μ
s
T ypically 2.5
μ
s
DAC Code Change All 1s to All 0s
3
3
10
2
100
3
3
10
2
100
3
3
10
2
100
μ
s max
μ
s max
nV secs typ
nV secs typ
dB typ
V
IN
=
±
3 V, 41.5 kHz Sine Wave
POWER REQUIREMENT S
As per ADC Section
NOT ES
1
T emperature ranges are as follows: A/B Versions, –40
°
C to +85
°
C; T Version, –55
°
C to +125
°
C.
2
V
OUT
(pk–pk) =
±
3 V.
3
SNR calculation includes distortion and noise components.
4
Using external sample and hold.
5
Measured with respect to RI DAC and includes bipolar offset error.
6
For capacitive loads greater than 50 pF a series resistor is required
(see INT ERNAL REFERENCE section).
7
Sample tested @ +25
°
C to ensure compliance.
Specifications subject to change without notice.
ORDE RING GUIDE
Relative
Accuracy
(LSB)
T emperature
Range
Package
Option*
Model
SNR
AD7868AN
AD7868AQ
AD7868BN
AD7868BQ
AD7868AR
AD7868BR
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
70 dB
70 dB
72 dB
72 dB
70 dB
72 dB
±
1/2 typ
±
1/2 typ
±
1 max
±
1 max
±
1/2 typ
±
1 max
N-24
Q-24
N-24
Q-24
R-28
R-28
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline IC).
DAC SECTION
AD7868
–3–
REV. B
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND = 0 V, RI DAC = +3 V and decoupled as shown in Figure 2, V
OUT
Load to AGND; R
L
= 2 k
, C
L
= 100 pF. All specifications T
MN
to T
MAX
unless otherwse noted.)
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