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參數(shù)資料
型號(hào): AD7884BP
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: LC2MOS 16-Bit, High Speed Sampling ADCs
中文描述: 2-CH 16-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 6/16頁
文件大小: 319K
代理商: AD7884BP
AD7884/AD7885
REV. C
–6–
PIN FUNCT ION DE SCRIPT ION
AD7884
AD7885
AD7885A
Description
V
INV
V
INV
V
INV
T his pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied +3 V reference.
T his is the negative reference input, and it can be obtained by using an external amplifier
to invert the positive reference input. In this case, the amplifier output is connected to
V
REF–.
See Figure 6.
T his is the analog input sense pin for the
±
3 volt analog input range on the AD7884 and
AD7885A.
T his is the analog input force pin for the
±
3 volt analog input range on the AD7884 and
AD7885A. When using this input range, the
±
5 V
IN
F and
±
5 V
IN
S pins should be tied to
AGND.
T his is the analog input pin for the
±
3 volt analog input range on the AD7885. When us-
ing this input range, the
±
5 V
IN
F and
±
5 V
IN
S pins should be tied to AGND.
T his is the analog input sense pin for the
±
5 volt analog input range on both the AD7884,
AD7885 and AD7885A.
T his is the analog input force pin for the
±
5 volt analog input range on both the AD7884,
AD7885 and AD7885A. When using this input range, the
±
3 V
IN
F and
±
3 V
IN
S pins
should be tied to AGND.
T his is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
T his is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
T his is the ground return for sample-and-hold section.
Negative supply for the 9-bit ADC.
Positive supply for the 9-bit ADC and all device logic.
T his asynchronous control input starts conversion.
Chip Select control input.
Read control input. T his is used in conjunction with
CS
to read the conversion result
from the device output latch.
High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
Busy output. T he Busy output goes low when conversion begins and stays low until it is
completed, at which time it goes high.
Sixteen-bit parallel data word output on the AD7884.
Eight-bit parallel data byte output on the AD7885.
Ground return for all device logic.
Reference force input.
Reference sense input. T he device operates from a +3 V reference.
V
REF–
V
REF–
V
REF–
±
3 V
IN
S
_
±
3 V
IN
S
±
3 V
IN
F
_
±
3 V
IN
F
±
3 V
IN
±
5 V
IN
S
±
5 V
IN
S
±
5 V
IN
S
±
5 V
IN
F
±
5 V
IN
F
±
5 V
IN
F
AGNDS
AGNDF
AV
DD
AV
SS
GND
V
SS
V
DD
CONVST
CS
RD
AGNDS
AGNDF
AV
DD
AV
SS
GND
V
SS
V
DD
CONVST
CS
RD
AGNDS
AGNDF
AV
DD
AV
SS
GND
V
SS
V
DD
CONVST
CS
RD
HBEN
HBEN
BUSY
BUSY
BUSY
DB0–DB15
DGND
V
REF+
F
V
REF+
S
DB0–DB7
DGND
V
REF+
F
V
REF+
S
DB0–DB7
DGND
V
REF+
F
V
REF+
S
相關(guān)PDF資料
PDF描述
AD7885 LC2MOS 16-Bit, High Speed Sampling ADCs
AD7885AAP LC2MOS 16-Bit, High Speed Sampling ADCs
AD7885ABP LC2MOS 16-Bit, High Speed Sampling ADCs
AD7885AN LC2MOS 16-Bit, High Speed Sampling ADCs
AD7885BN LC2MOS 16-Bit, High Speed Sampling ADCs
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