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參數資料
| 型號： | AD7896SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIP |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-8 |
| 文件頁數： | 11/12頁 |
| 文件大小： | 367K |
| 代理商： | AD7896SQ |
AD7896
REV. B
–11–
Dynamic Performance (Mode 1 Only)
With a combined conversion and acquisition time of 9.5
μ
s, the
AD7896 is ideal for wide bandwidth signal processing applica-
tions. These applications require information on the ADC’s ef-
fect on the spectral content of the input signal. Signal to (Noise
+ Distortion), Total Harmonic Distortion, Peak Harmonic or
Spurious Noise and Intermodulation Distortion are all specified.
Figure 11 shows a typical FFT plot of a 10 kHz, 0 V to +3.3 V
input after being digitized by the AD7896 operating at a
102.4 kHz sampling rate. The Signal to (Noise + Distortion)
Ratio is 71.5 dB and the Total Harmonic Distortion is –83 dB.
–0
–120
51200
–60
–100
10240
–80
0
–20
–40
40960
30720
20480
FREQUENCY – Hz
F
SAMPLE
= 102.4 kHz
F
SNR = 71.54dB
THD = –82.43dB
d
Figure 11. AD7896 FFT Plot
Effective Number of Bits
The formula for Signal to (Noise + Distortion) Ratio (See Ter-
minology section) is related to the resolution or number of bits
in the converter. Rewriting the formula, below, gives a measure
of performance expressed in effective number of bits (N):
N
= (
SNR
1.76)/6.02
where
SNR
is Signal to (Noise + Distortion) Ratio.
The effective number of bits for a device can be calculated from
its measured Signal to (Noise + Distortion) Ratio. Figure 12
shows a typical plot of effective number of bits versus frequency
for the AD7896 from dc to f
SAMPLING
/2. The sampling fre-
quency is 102.4 kHz. The plot shows that the AD7896 converts
an input sine wave of 51.2 kHz to an effective numbers of bits of
11.25 which equates to a Signal to (Noise + Distortion) level
of
69 dB.
12.00
0
51.2
25.6
11.75
11.50
11.25
11.00
INPUT FREQUENCY – kHz
E
Figure 12. Effective Number of Bits vs. Frequency
Power Considerations
In the automatic power-down mode then the part may be oper-
ated at a sample rate which is considerably less than 100 kHz. In
this case the power consumption will be reduced and will de-
pend on the sample rate. Figure 13 shows a graph of the power
consumption versus sampling rates from 10 Hz to 1 kHz in the
automatic power-down mode. The conditions are 2.7 V supply
25
°
C, serial clock frequency of 8.33 MHz and the data was read
after conversion.
200
0
1000
120
40
100
80
10
160
SAMPLING RATE IN Hz
P
μ
W
F
SCLK
= 8.33 MHz
Figure 13. Power vs. Sample Rate in Auto Power-Down
Mode
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