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參數資料
| 型號： | AD7898AR-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead Package |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 15/16頁 |
| 文件大?。?/td> | 184K |
| 代理商： | AD7898AR-3 |
–15–
REV. 0
AD7898
TMS320C5x/C54x to AD7898 Interface
The serial interface on the TMS320C5x/C54x uses a continu-
ous serial clock and frame synchronization signal to synchronize
the data transfer operations with peripheral devices like the
AD7898. The
CS
input allows easy interfacing between the
TMS320C5x/C54x and the AD7898 without any glue logic
required. The serial port of the TMS320C5x/C54x is set up to
operate in burst mode with internal CLKX (TX serial clock)
and FSX (TX frame sync). The serial port control register (SPC)
must have the following setup: FO = 0, FSM = 1, MCM = 1,
and TXM = 1. The format bit, FO, may be set to 1 to set the
word length to 8 bits, in order to implement the power-down
modes on the AD7898.
The connection diagram is shown in Figure 17. It should be
noted that for signal processing applications, it is imperative that
the frame synchronization signal from the TMS320C5x/C54x
will provide equidistant sampling. The V
DRIVE
pin of the AD7898
takes the same supply voltage as that of the TMS320C5x/C54x.
This allows the ADC to operate at a higher voltage than the
serial interface, i.e., TMS320C5x/C54x, if necessary.
AD7898
*
SDATA
SCLK
CS
TMS320C5x/C54x
*
CLKX
*
ADDITIONAL PINS OMITTED FOR CLARITY
CLKR
DR
FSX
FSR
V
DRIVE
V
DD
Figure 17 AD7898 to TMS320C5x Interface
AD7898 to ADSP-21xx Interface
The ADSP-21xx family of DSPs are interfaced directly to the
AD7898 without any glue logic required. The V
DRIVE
pin of the
AD7898 takes the same supply voltage as that of the ADSP-21xx.
This allows the ADC to operate at a higher voltage than the
serial interface, i.e., ADSP-21xx, if necessary.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0,
ITFS = 1.
To implement the power-down mode, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 18. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS
set as an output and RFS set as an input. The DSP operates in
Alternate Framing Mode and the SPORT control register is set
up as described. The Frame Synchronization signal generated
on the TFS is tied to
CS
and as with all signal processing applica-
tions equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC and, under certain conditions, equidistant sampling may
not be achieved.
AD7898
*
SCLK
CS
SDATA
V
DRIVE
ADSP-21xx
*
SCLK
*
ADDITIONAL PINS OMITTED FOR CLARITY
DR
RFS
TFS
V
DD
Figure 18. AD7898 to ADSP-21xx Interface
The Timer registers etc. are loaded with a value that will provide
an interrupt at the required sample interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and hence the reading
of data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given, (i.e.,
AX0 = TX0), the state of the SCLK is checked. The DSP will
wait until the SCLK has gone high, low and high before trans-
mission will start. If the timer and SCLK values are chosen such
that the instruction to transmit occurs on or near the rising edge
of SCLK, then the data may be transmitted or it may wait until
the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, a
SCLK of 2 MHz is obtained, and eight master clock periods will
elapse for every 1 SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs will occur between interrupts
and subsequently between transmit instructions. This situation
will result in nonequidistant sampling as the transmit instruction
is occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling
will be implemented by the DSP.
AD7898 to DSP56xxx Interface
The connection diagram in Figure 19 shows how the AD7898
can be connected to the SSI (Synchronous Serial Interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is oper-
ated in Synchronous Mode (SYN bit in CRB = 1) with internally
generated 1-bit clock period frame sync for both TX and RX
(bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to
16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To implement
the power-down mode on the AD7898 then the word length
can be changed to 8 bits by setting bits WL1 = 0 and WL0 = 0
in CRA. It should be noted that for signal processing applica-
tions, it is imperative that the frame synchronization signal
from the DSP56xxx will provide equidistant sampling. The
V
DRIVE
pin of the AD7898 takes the same supply voltage as that
of the DSP56xxx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., DSP56xxx, if necessary.
AD7898
*
SDATA
SCLK
CS
DSP56xxx
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
SCK
SRD
SC2
V
DRIVE
V
DD
Figure 19. AD7898 to DSP56xxx Interface
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