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參數資料
| 型號： | AD7898AR-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead Package |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 3/16頁 |
| 文件大小： | 184K |
| 代理商： | AD7898AR-3 |
–3–
REV. 0
AD7898
Parameter
Limit at T
MIN
, T
MAX
Unit
Description
Mode 0 Operation
t
1
t
2
t
3
40
26
2
26
2
30
2
30
2
60
3
70
3
20
50
4
3.3
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
μ
s
CONVST
Pulsewidth
SCLK High Pulsewidth, V
DRIVE
= 5 V
±
5%
SCLK Low Pulsewidth, V
DRIVE
= 5 V
±
5%
SCLK High Pulsewidth V
DRIVE
= 2.7 V to 3.6 V
SCLK Low Pulsewidth V
DRIVE
= 2.7 V to 3.6 V
Data Access Time after Falling Edge of SCLK, V
DRIVE
= 5 V
±
5%
Data Access Time after Falling Edge of SCLK, V
DRIVE
= 2.7 V to 3.6 V
Data Hold Time after Falling Edge of SCLK
Bus Relinquish Time after Falling Edge of SCLK
t
4
t
4
t
5
t
6
t
CONVERT
Mode 1 Operation
f
SCLK5
1
3.7
16
×
t
SCLK
4.33
100
70
40
80
108
108
60
20
60
4.33
kHz min
MHz max
t
CONVERT
t
SCLK
= 1/f
SCLK
f
SCLK
= 3.7 MHz
Minimum Quiet Time Required between Conversions
CS
to SCLK Setup Time
Delay from
CS
Until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Power-Down Mode
μ
s max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μ
s max
t
QUIET
t
2
t
33
t
43
t
5
t
6
t
7
t
84
t
POWER-UP
NOTES
1
Sample tested at 25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
The SCLK maximum frequency is 15 MHz for Mode 0 operation for 220 kSPS throughput with V
= 5 V
±
= 2.7 V to 3.6 V.
The mark/space ratio for SCLK is specified for at least 40% high time (with corresponding 60% low time) or 40% low time (with corresponding 60% high time). As
the SCLK frequency is reduced, the mark/space ratio may vary, provided limits are not exceeded. Care must be taken when interfacing to account for the data access
time, t
, and the set-up time required for the users processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with.
See Serial Interface section.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
and t
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
and t
8
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
5
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(V
DD
= 4.75 V to 5.25 V; V
DRIVE
= 2.7 V to 5.25 V; REF IN = 2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
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