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參數資料
| 型號： | AD7921ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數： | 15/28頁 |
| 文件大?。?/td> | 312K |
| 代理商： | AD7921ARM |
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AD7911/AD7921
CIRCUIT INFORMATION
The AD7911/AD7921 are fast, 2-channel, 10-/12-bit, single
supply, analog-to-digital converters (ADCs), respectively. The
parts can be operated from a 2.35 V to 5.25 V supply. When
operated from either a 5 V supply or a 3 V supply, the
AD7911/AD7921 are capable of throughput rates of 250 kSPS
when provided with a 5 MHz clock.
Rev. 0 | Page 15 of 28
The AD7911/AD7921 provide the user with an on-chip track-
and-hold, an ADC, and a serial interface, all housed in a tiny 8-
lead TSOT package or an 8-lead MSOP package, which offer the
user considerable space-saving advantages over alternative
solutions. The serial clock input accesses data from the parts,
controls the transfer of data written to the ADC, and provides
the clock source for the successive approximation ADC. The
analog input range is 0 to V
DD
. An external reference is not
required for the ADC, and neither is there a reference on-chip.
The reference for the AD7911/AD7921 is derived from the
power supply and, therefore, gives the widest dynamic input
range.
The AD7911/AD7921 feature a power-down option that allows
power saving between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7911/AD7921 are 10-/12-bit successive approximation
ADCs based around a charge redistribution DAC. Figure 19 and
Figure 20 show simplified schematics of the ADC. Figure 19
shows the ADC during its acquisition phase. SW2 is closed and
SW1 is in Position A, the comparator is held in a balanced
condition, and the sampling capacitor acquires the signal on the
selected V
IN
channel.
0
COMPARATOR
ACQUISITION
PHASE
V
DD
/2
SW2
SW1
V
IN0
V
IN1
SAMPLING
CAPACITOR
AGND
A
B
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
Figure 19. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 20), SW2 opens
and SW1 moves to Position B, causing the comparator to
become unbalanced. The control logic and the charge
redistribution DAC are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. Figure 21 shows the ADC
transfer function.
0
COMPARATOR
CONVERSION
PHASE
V
DD
/2
SW2
SW1
V
IN0
V
IN1
SAMPLING
CAPACITOR
AGND
A
B
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
Figure 20. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7911/AD7921 is straight binary.
The designed code transitions occur at the successive integer
LSB values, that is, 1 LSB, 2 LSB, and so on. The LSB size is
V
DD
/4096 for the AD7921 and V
DD
/1024 for the AD7911. The
ideal transfer characteristic for the AD7911/AD7921 is shown
in Figure 21.
0
000...000
0V
A
ANALOG INPUT
111...111
111...110
000...001
111...000
011...111
000...010
1LSB = V
DD
/4096 (AD7921)
1LSB = V
DD
/1024 (AD7911)
+V
DD
– 1LSB
1LSB
Figure 21. AD7911/AD7921 Transfer Characteristic
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