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參數資料
| 型號： | AD7921ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數： | 19/28頁 |
| 文件大小： | 312K |
| 代理商： | AD7921ARM |
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AD7911/AD7921
Rev. 0 | Page 19 of 28
0
INVALID DATA
THREE-STATE
INVALID DATA
THREE-STATE
1
CS
SCLK
DIN
DOUT
2
10
16
Figure 27. Entering Power- Down Mode
0
1
10
THE PART BEGINS
TO POWER UP
THE PART GOES
INTO TRACK
THE PART IS FULLY
POWERED UP WITH V
IN
FULLY ACQUIRED
5
A
16
1
16
SCLK
CS
DIN
CHANNEL FOR NEXT CONVERSION
CHANNEL FOR NEXT CONVERSION
DOUT
INVALID DATA
CONVERSION RESULT
Figure 28. Exiting Power-Down Mode
POWER-UP TIME
The power-up time of the AD7911/AD7921 is 1 μs, which
means that with any frequency of SCLK up to 5 MHz, one
dummy cycle is always sufficient to allow the device to power
up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, t
QUIET
, must still be allowed from the point at which the
bus goes back into three-state after the dummy conversion to
the next falling edge of CS. When running at a 250 kSPS
throughput rate, the AD7911/AD7921 power up and acquire a
signal within ±1 LSB in one dummy cycle.
When powering up from power-down mode with a dummy
cycle, as in Figure 28, the track-and-hold that was in hold mode
while the part was powered down returns to track mode on the
fifth SCLK falling edge that the part receives after the falling
edge of CS. This is shown as point A in Figure 28. At this point,
the part starts to acquire the signal on the channel selected in
the current dummy conversion.
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire V
IN
, it does not necessarily
mean that a full dummy cycle of 16 SCLKs must always elapse
to power up the device and acquire V
IN
fully. 1μs is sufficient to
power up the device and acquire the input signal. For example,
if a 5 MHz SCLK frequency was applied to the ADC, the cycle
time would be 3.2 μs. In one dummy cycle, 3.2 μs, the part
would be powered up and V
IN
acquired fully. However, after 1 μs
with a 5 MHz SCLK, only 5 SCLK cycles would have elapsed. At
this stage, the ADC would be fully powered up. In this case, CS
can be brought high after the 10th SCLK falling edge and
brought low again after a time, t
QUIET
, to initiate the conversion.
When power supplies are first applied to the AD7911/AD7921,
the ADC can power up in either power-down mode or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if the user wants to
keep the part in power-down mode while not in use and to
power up in power-down mode, then the dummy cycle can be
used to ensure that the device is in power-down mode by
executing a cycle such as that shown in Figure 27.
Once supplies are applied to the AD7911/AD7921, the power-
up time is the same as when powering up from the power-down
mode. It takes the part approximately 1 μs to power up fully in
normal mode. It is not necessary to wait 1 μs before executing a
dummy cycle to ensure the desired mode of operation. Instead,
the dummy cycle can occur directly after power is supplied to
the ADC. If the first valid conversion is then performed directly
after the dummy conversion, care must be taken to ensure that
adequate acquisition time has been allowed. When the ADC
powers up initially after supplies are applied, the track-and-hold
is in hold. It returns to track on the fifth SCLK falling edge that
the part receives after the falling edge of CS.
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