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參數(shù)資料
型號(hào): AD7921ARM
廠商: ANALOG DEVICES INC
元件分類(lèi): ADC
英文描述: 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: MO-187AA, MSOP-8
文件頁(yè)數(shù): 20/28頁(yè)
文件大小: 312K
代理商: AD7921ARM
AD7911/AD7921
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7911/AD7921 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 29 shows how, as the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over
time drops accordingly.
Rev. 0 | Page 20 of 28
For example, if the AD7911/AD7921 are operating in a
continuous sampling mode with a throughput rate of 50 kSPS
and a SCLK of 5 MHz (V
DD
= 5 V) and the devices are placed in
power-down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 20 mW (V
DD
= 5 V). If one dummy
cycle powers up the part between conversions (3.2 μs), and the
remaining conversion time is another cycle (3.2 μs), then the
AD7911/AD7921 dissipate 20 mW for 6.4 μs during each
conversion cycle. If the throughput rate is 50 kSPS and the cycle
time is 20 μs, then the average power dissipated during each
cycle is
(6.4/20) × (20 mW) = 6.4 mW
If V
DD
= 3 V, SCLK= 5 MHz, and the device is again in power-
down mode between conversions, then the power dissipation
during normal operation is 6 mW. The AD7911/AD7921 now
dissipate 6 mW for 6.4 μs during each conversion cycle. With a
throughput rate of 50 kSPS, the average power dissipated during
each cycle is
(6.4/20) × (6 mW) = 1.92 mW
In the previous examples, the power dissipation when the part is
in power-down mode has not been taken into account, because
the shutdown current is so low that it does not have any effect
on the overall power dissipation value. Figure 29 shows the
power consumption versus throughput rate when using the
power-down mode between conversions with both 5 V and 3 V
supplies.
Power-down mode is intended for use with throughput rates of
approximately 120 kSPS and under, because higher sampling
rates do not have a power saving in power-down mode.
0.01
100
10
1
0.1
0
135
120
105
90
75
60
45
THROUGHPUT (kSPS)
30
15
0
P
V
DD
= 5V, SCLK = 5MHz
V
DD
= 3V, SCLK = 5MHz
Figure 29. Power Consumption vs. Throughput Rate
相關(guān)PDF資料
PDF描述
AD7921ARM-REEL 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
AD7921ARM-REEL7 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
AD7921AUJ-R2 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
AD7921AUJ-REEL7 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
AD7911 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
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