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參數資料
| 型號： | AD7993BRU-0 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP |
| 中文描述： | 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153-AB, TSSOP-16 |
| 文件頁數： | 15/27頁 |
| 文件大小： | 277K |
| 代理商： | AD7993BRU-0 |
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AD7994/AD7993
–15–
REV. PrF
PRELIMINARY TECHNICAL DATA
INTERNAL REGISTER STRUCTURE
The AD7994/AD7993 contains seventeen internal regis-
ters, as shown in Figure 9, that are used to store conver-
sion results, high and low conversion limits, and to
configure and control the device. Sixteen are data registers
and one is an address pointer register.
Figure 9. AD7994/AD7993 Register Structure
Each data register has an address which is pointed to by
the Address Pointer register when communicating with it.
The Conversion Result Register is the only data register
that is read only.
Table II. Address Pointer Register
C4
C3
C2
C1
P3
P2
P1
P0
0
0
0
0
Register Select
ADDRESS POINTER REGISTER
The Address Pointer register itself does not have, nor does
it require, an address, as it is the register to which the first
data byte of every Write operation is written automatically.
The Address Pointer Register is an 8-bit register in which
the four LSBs are used as pointer bits to store an address
that points to one of the data registers of the AD7994/
AD7993, while the four MSBs are used as command bits
when operating in Mode 2 (see Modes of Operation sec-
tion). The first byte following each write address is the
address of one of the data registers, which is stored in the
Address Pointer Register, and selects the data register to
which subsequent data bytes are written. Only the four
LSBs of this register are used to select a data register. On
Power up the Address Point register contains all 0’s,
pointing to the Conversion Result Register.
CONFIGURATION
REGISTER
ADDRESS
POINTER
REGISTER
SERIAL BUS INTERFACE
SDA
SCL
D
A
T
A
DATALOW
REGISTER CH2
DATAHIGH
REGISTER CH2
DATALOW
REGISTER CH1
HYSTERESIS
REGISTER CH1
DATAHIGH
REGISTER CH1
CYCLE TIMER
REGISTER
ALERT STATUS
REGISTER
CONVERSION
RESULT REGISTER
HYSTERESIS
REGISTER CH2
DATAHIGH
REGISTER CH3
DATALOW
REGISTER CH3
HYSTERESIS
REGISTER CH3
DATAHIGH
REGISTER CH4
DATALOW
REGISTER CH4
HYSTERESIS
REGISTER CH4
Table III. AD7994/AD7993 Register Addresses
P3
P2
P1
P0
Registers
0
0
0
0
Conversion Result Register (Read)
0
0
0
1
Alert Status Register (Read/Write)
0
0
1
0
Configuration Register (Read/Write)
0
0
1
1
Cycle Timer Register (Read/Write)
0
1
0
0
DATA
LOW
Reg CH1 (Read/Write)
DATA
HIGH
Reg CH1 (Read/Write)
Hysteresis Reg CH1 (Read/Write)
0
1
0
1
0
1
1
0
0
1
1
1
DATA
LOW
Reg CH2 (Read/Write)
DATA
HIGH
Reg CH2 (Read/Write)
Hysteresis Reg CH2 (Read/Write)
1
0
0 0
1
0
0 1
1
0
1
0
DATA
LOW
Reg CH3 (Read/Write)
DATA
HIGH
Reg CH3 (Read/Write)
Hysteresis Reg CH3 (Read/Write)
1
0
1
1
1
1
0
0
1
1
0
1
DATA
LOW
Reg CH4 (Read/Write)
DATA
HIGH
Reg CH4 (Read/Write)
Hysteresis Reg CH4 (Read/Write)
1
1
1
0
1
1
1
1
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