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參數(shù)資料
型號: AD7993BRU-0
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
中文描述: 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝: MO-153-AB, TSSOP-16
文件頁數(shù): 16/27頁
文件大小: 277K
代理商: AD7993BRU-0
AD7994/AD7993
–16–
REV. PrF
PRELIMINARY TECHNICAL DATA
Bit
D7-D4 CH4-CH1
Mnemonic
Comment
These four channel address bits select the analog input channel(s) to be converted on.
A 1 in any of bits D7 to D4 selects a channel for conversion. If more than one channel bit is
set to 1 then the AD7994/AD7993 will sequence through the selected channels, starting with
the lowest channel. All unused channels should be set to zero. Table V shows how these four
channel address bits are decoded.
Prior to initiating a conversion a channel(s) must be
selected in the Configuration Register.
The value written to this bit of the Control Register determines whether the filtering on SDA
and SCL is enabled or to be bypassed. If this bit is a 1 then the the filtering is enabled, if it is
a 0, then the filtering is bypassed.
The hardware ALERT function is enabled if this bit is set to 1 and disabled if set to 0. This bit
is used in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin will
act as an ALERT or a BUSY output. (See Table VI.)
This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/BUSY
output, pin 13, will act as an ALERT or BUSY output (see TABLE V1), or if pin 13 is
configured as an ALERT output pin, if it is to be reset. When reading the Configuration
registerD1 will always be a 0 when D2 is a 1.
This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is
configured as an ALERT or BUSY output. It is active low if this bit is set to 0, and it is active
high if set to 1.
D3
FLTR
D2
ALERT EN
D1
BUSY/ALERT
D0
BUSY/ALERT
POLARITY
CONFIGURATION REGISTER
The Configuration Register is an 8-bit read/write register that is used to set the operating modes of the AD7994/
AD7993. The bit functions of all 8 bits of the Configuration Register are outlined in Table IV.
Table IV. Configuration Register Bit Function Description
D7
D6
D5
D4
D3
D2
D1
D0
CH4
CH3
CH2 CH1
FLTR
ALERT EN
BUSY/ALERT
ALERT/BUSY POLARITY
0*
0*
0*
0*
1*
0*
0*
0*
*Default settings at Power-up
相關(guān)PDF資料
PDF描述
AD7993 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
AD7994 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
AD7993BRU-1 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
AD7997 8-Channel, 10- and 12-Bit ADCs with I2CCompatible
AD7997BRU-0 8-Channel, 10- and 12-Bit ADCs with I2CCompatible
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