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參數(shù)資料
| 型號： | AD7993BRU-0 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP |
| 中文描述： | 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153-AB, TSSOP-16 |
| 文件頁數(shù)： | 17/27頁 |
| 文件大小： | 277K |
| 代理商： | AD7993BRU-0 |
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AD7994/AD7993
–17–
REV. PrF
PRELIMINARY TECHNICAL DATA
CONVERSION RESULT REGISTER
The Conversion Result Register is a 16-bit read-only reg-
ister which stores the conversion result from the ADC in
Straight Binary format. A Two Byte read is necessary to
read data from this register. Table VIIa shows the contents
of the first byte to be read while Table VIIb show the
contents of the second byte to be read from AD7994/
AD7993.
Table VIIa. Conversion Value Register (First Read)
The AD7994/AD7993 conversion result consists of an
Alert_Flag bit, a leading zero, two Channel Identifier bits
and the 12-/10- bit data result. For the AD7993 the two
LSBs (D1 and D0) of the second read will contain two
zeros.
The Alert_Flag bit indicates whether the conversion result
being read or any other channel result has violated the
limit registers associated with it. The Master may wish to
read the ALERT Status register to obtain more informa-
tion on where the ALERT occurred if this Alert_Flag bit
is set.
This is followed by a leading zero and the two Channel
Indentifier bits indicating which channel the conversion
result corresponds to. The 12-/10-bit conversion result
then follows MSB first.
Table VI. ALERT/BUSY Function
D2
D1
ALERT/BUSY Pin Configuration
0
0
Pin does not provide any interrupt signal.
0
1
Pin configured as a BUSY output.
1
0
Pin configured as an ALERT output.
1
1
Resets ALERT output pin, Alert_Flag bit in
Conversion Result Reg, and entire Alert
Status Reg ( if any active).
Note 1:-
The AD7994/AD7994 converts on the selected channel in the Sequence in ascending order, starting with the
lowest channel in the sequence.
Table V. Channel Selection
D7
D6
D5 D4
Analog Input Channel
0
0
0 0
No channel selected, see Address Pointer Byte, Mode 2
0
0
0 1
Convert on V
IN
1
Convert on V
IN
2
Sequence between V
IN
1 and V
IN
2
Convert on V
IN
3
Sequence between V
IN
1 and V
IN
3
Sequence between V
IN
2 and V
IN
3
Sequence between V
IN
1, V
IN
2 and V
IN
3
Convert on V
IN
4
Sequence between V
IN
1 and V
IN
4
Sequence between V
IN
2 and V
IN
4
Sequence between V
IN
1, V
IN
2 and V
IN
4
Sequence between V
IN
3 and V
IN
4
Sequence between V
IN
1, V
IN
3 and V
IN
4
Sequence between V
IN
2, V
IN
3 and V
IN
4
Sequence between V
IN
1, V
IN
2, V
IN
3 and V
IN
4
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
Alert_Flag
1
Zero CH
ID1
CH
ID0
Channel# Result
0/1
0
0
0
Channel 1(V
IN
1)
Channel 2(V
IN
2)
Channel 3(V
IN
3)
Channel 4(V
IN
4)
0/1
0
0
1
0/1
0
1
0
0/1
0
1
1
Table VIIb. Conversion Value Register (Second Read)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1/0
B0/0
D15
D14
D13
D12
D11
D10
D9
D8
Alert_Flag Zero CH
ID1
CH
ID0
MSB B10
B9
B8
If 1/1 is written to bits D2/D1 in the configuration Regis-
ter to reset the ALERT pin, the Alert Flag bit and the
Alert Status Register; the contents of the Configuration
Register will read 1/0 for D2/D1 respectively if read back.
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