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參數(shù)資料
型號: AD7993BRU-0
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
中文描述: 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝: MO-153-AB, TSSOP-16
文件頁數(shù): 21/27頁
文件大小: 277K
代理商: AD7993BRU-0
AD7994/AD7993
–21–
REV. PrF
PRELIMINARY TECHNICAL DATA
WRITING TO THE AD7994/AD7993
Depending on the register being written to, there are two
different writes for the AD7994/AD7993.
Writing to the Address Pointer Register for a Subse-
quent Read
In order to read from a particular register, the Address
Pointer register must first contain the address of that reg-
ister. If it does not, the correct address must be written to
the Address pointer register by performing a single-byte
write operation, as shown in Figure 10. The write opera-
tion consists of the serial bus address followed by the ad-
dress pointer byte. No data is written to any of the data
registers. A read operation maybe subsequently performed
to read the register of interest.
Writing a Single Byte of Data to the Alert Status Regis-
ter or Cycle Register
The Configuration Register and Cycle Register are both
8-bit registers, so only one byte of data can be written to
each. Writing a single byte of data to one of these registers
consists of the serial bus write address, the chosen data
register address written to the Address Pointer Register,
followed by the data byte written to the selected data reg-
ister. This is illustrated in Figure 11.
Writing two Bytes of Data to a Limit Register, Hyster-
esis Register or Configuration register.
Each of the four Limit Registers are 12-bit registers, so
two bytes of data are required to write a value to any one
of them. Writing two bytes of data to one of these registers
consists of the serial bus write address, the chosen Limit
Register address written to the Address Pointer Register,
followed by two data bytes written to the selected data
register. This is illustrated in Figure 12.
SERIAL INTERFACE
Control of the AD7994/AD7993 is carried out via the
I
2
C-compatible serial bus. The AD7994/AD7993 is con-
nected to this bus as a slave device, under the control of a
master device, e.g. the processor.
SERIAL BUS ADDRESS
Like all I
2
C-compatible devices, the AD7994/AD7993 has
a 7-bit serial address. The three MSBs of this address for
the AD7994/AD7993 are set to 010. The AD7994/
AD7993 comes in two versions, the AD7994-0/AD7993-0
and AD7994-1/AD7993-1. The two versions have three
different I
2
C addresses available which are selected by
either tying the Address Select pin, AS, to GND, to V
DD
or letting the pin float (see Table I). By giving different
addresses for the two versions, up to five AD7994/
AD7993 devices can be connected to a single serial bus,
or the addresses can be set to avoid conflicts with other
devices on the bus. See I
2
C Address Selection table.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line,
SCL, remains high. This indicates that an address/data
stream will follow. All slave peripherals connected to
the serial bus respond to the START condition, and
shift in the next 8 bits, consisting of a 7-bit address
(MSB first) plus a R/
W
bit, which determines the di-
rection of the data transfer, i.e. whether data will be
written to or read from the slave device.
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices on the
bus now remain idle whilst the selected device waits for
data to be read from or written to it. If the R/
W
bit is a
0 then the master will write to the slave device. If the
R/
W
bit is a 1 the master will read from the slave de-
vice.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the receiver of data. Transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
Figure 10. Writing to the Address Pointer Register to se-
lect a register for a subsequent Read operation
high transition when the clock is high may be inter-
preted as a STOP signal.
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the mas-
ter device will pull the data line high during the low
period before the 9th clock pulse. This is known as No
Acknowledge. The master will then take the data line
low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation, because the type of opera-
tion is determined at the beginning and cannot subse-
quently be changed without starting a new operation.
SDA
ACK. BY
AD7994/3
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
AD7994/3
1
9
1
C4
C3
C2
P2
P1
P0
R/
A0
A1
A2
A3
0
0
SCL
STOP BY
MASTER
1
C1
P3
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