- 您現在的位置：買賣IC網 > PDF目錄373939 > AD8176ABPZ (ANALOG DEVICES INC) 475 MHz, Triple 16 】 9 Video Crosspoint Switch PDF資料下載
參數資料
| 型號： | AD8176ABPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 475 MHz, Triple 16 】 9 Video Crosspoint Switch |
| 中文描述： | 16-CHANNEL, CROSS POINT SWITCH, PBGA676 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AAL-1, BGA-676 |
| 文件頁數： | 23/32頁 |
| 文件大小： | 489K |
| 代理商： | AD8176ABPZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Preliminary Technical Data
AD8176
For a practical example, refer to Figure 23. (Note that the output
pulses have been slightly shifted with respect to each other for
clarity.)
Rev. PrA | Page 23 of 32
1.4V
NEGATIVE
PHASE
POSITIVE
PHASE
VBLK = 0V
VOCM_CMENCOFF = 0.7V
0V
0
Figure 23. Output at the AD8176 pins for 0 V to 0.7 V Input Differential Pulse,
VBLK = 0 V, VOCM_CMENCOFF = 0.7 V
The input to the AD8176 is a differential pulse with a low level
of 0 V and a high level of 0.7 V. VBLK is set to 0 V, while
VOCM_CMENCOFF is set to 0.7 V. With this choice of values,
the positive and negative output phases are overlapped, (with
the positive phase ranging from 0 V to 1.4 V, and the negative
phase ranging from 1.4 V to 0 V, respectively). The supplies are
set to +3 V/2 V to be in compliance with output headroom
requirements.
The voltage on the positive output phase for a 0 V differential
input is equal to the voltage on VBLK, for all cases when VBLK
and VOCM_CMENCOFF differ by more than ±100 mV.
PROGRAMMING
The AD8176 has two options for changing the programming of
the crosspoint matrix. In the first option, a serial word of 45 bits
can be provided that updates the entire matrix each time. The
second option allows for changing a single output’s
programming via a parallel interface. The serial option requires
fewer signals, but more time (clock cycles) for changing the
programming; the parallel programming technique requires
more signals, but allows for changing a single output at a time,
therefore requiring fewer clock cycles.
Serial Programming Description
The serial programming mode uses the device pins CS, CLK,
SERIN, UPDATE, and SER/PAR. The first step is to enable the
CLK on by pulling CS low. Next, SER/PAR is pulled low to
enable the serial programming mode. The parallel clock WE
should be held high during the entire serial programming
operation.
The UPDATE signal should be high during the time that data is
shifted into the device’s serial port. Although the data still shifts
in when UPDATE is low, the transparent, asynchronous latches
allow the shifting data to reach the matrix. This causes the
matrix to try to update to every intermediate state as defined by
the shifting data.
The data at SERIN is clocked in at every falling edge of CLK. A
total of 45 bits must be shifted in to complete the programming.
A total of five bits must be supplied for each of the nine RGB
output channels
an output enable bit (D4) and four bits (D3 to
D0) which determine the input channel. If D4 is low (output
disabled), the four associated bits (D3 to D0) do not matter,
because no input will be switched to that output.
The most-significant-output-address data is shifted in first, with
the enable bit (D4) shifted in first, followed by the input address
(D3 to D0) entered sequentially with D3 first and D0 last. Each
remaining output is programmed sequentially, until the least-
significant-output-address data is shifted in. At this point,
UPDATE can be taken low, which causes the programming of
the device according to the data that was just shifted in. The
UPDATE latches are asynchronous and when UPDATE is low,
they are transparent.
If more than one AD8176 device is to be serially programmed
in a system, the SEROUT signal from one device can be
connected to the SERIN of the next device to form a serial
chain. All of the CLK, UPDATE, and SER/PAR pins should be
connected in parallel and operated as described above. The
serial data is input to the SERIN pin of the first device of the
chain, and it will ripple through to the last. Therefore, the data
for the last device in the chain should come at the beginning of
the programming sequence. The length of the programming
sequence is 45 bits times the number of devices in the chain. CS
gates the CLK and UPDATE signals, so that when CS is held
high both CLK and UPDATE are held in their inactive high
state, while when CS is held low, both CLK and UPDATE
function normally.
Parallel Programming Description
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification of
a single output or more at a time. Since this takes only one
WE/UPDATE cycle, significant time savings can be realized by
using parallel programming.
One important consideration in using parallel programming is
that the RST signal does not reset all registers in the AD8176.
When taken low, the RST signal only sets each output to the
disabled state. This is helpful during power-up to ensure that
two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device
generally have random data, even though the RST signal has
been asserted. If parallel programming is used to program one
output, then that output will be properly programmed, but the
rest of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up. This ensures that
the programming matrix is always in a known state. From then
on, parallel programming can be used to modify a single output
or more at a time.
相關PDF資料 |
PDF描述 |
|---|---|
| AD8178 | 450 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8178ABPZ1 | 450 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8178-EVALZ1 | 450 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD817 | High Speed, Low Power Wide Supply Range Amplifier(高速,低功耗,寬電源范圍放大器) |
| AD8180-EB | 750 MHz, 3.8 mA 10 ns Switching Multiplexers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD8176-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:475 MHz, Triple 16 】 9 Video Crosspoint Switch |
| AD8177 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8177ABPZ | 功能描述:IC VIDEO CROSSPOINT SWIT 676BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:- 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，FCBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8177-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8178 | 制造商:AD 制造商全稱:Analog Devices 功能描述:450 MHz, Triple 16 】 5 Video Crosspoint Switch |
發布緊急采購，3分鐘左右您將得到回復。