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參數資料
| 型號： | AD8176ABPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 475 MHz, Triple 16 】 9 Video Crosspoint Switch |
| 中文描述： | 16-CHANNEL, CROSS POINT SWITCH, PBGA676 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AAL-1, BGA-676 |
| 文件頁數： | 24/32頁 |
| 文件大?。?/td> | 489K |
| 代理商： | AD8176ABPZ |
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AD8176
Preliminary Technical Data
In similar fashion, if UPDATE is taken low after initial power-
up, the random power-up data in the shift register will be
programmed into the matrix. Therefore, in order to prevent the
crosspoint from being programmed into an unknown state, do
not apply a logic level to UPDATE after power is initially
applied. Programming the full shift register once to a desired
state, by either serial or parallel programming after initial
power-up, eliminates the possibility of programming the matrix
to an unknown state.
To change an output’s programming via parallel programming,
CS should be taken low, while SER/PAR and UPDATE should
be taken high. The serial programming clock, CLK, should be
left high during parallel programming. The parallel clock, WE,
should start in the high state. The 4-bit address of the output to
be programmed should be put on A3 to A0. Data Bit D3 to Data
Bit D0 should contain the information that identifies the input
that gets programmed to the output that is addressed. Data Bit
D4 determines the enabled state of the output. If D4 is low
(output disabled), then the data on D3 to D0 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low
transition of the WE signal. The matrix will not be programmed,
however, until the UPDATE signal is taken low. It is thus
possible to latch in new data for several or all of the outputs first
via successive negative transitions of WE while UPDATE is held
high, and then have all the new data take effect when UPDATE
goes low. This is the technique that should be used when
programming the device for the first time after power-up when
using parallel programming.
Reset
When powering up the AD8176, it is usually desirable to have
the outputs come up in the disabled state. The RST pin, when
taken low, causes all outputs to be in the disabled state.
However, the RST signal does not reset all registers in the
AD8176. This is important when operating in the parallel
programming mode. Please refer to that section for information
about programming internal registers after power-up. Serial
programming programs the entire matrix each time, so no
special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply a logic low
signal to UPDATE initially after power-up. The shift register
should first be loaded with the desired data, and only then can
the UPDATE be taken low to program the device.
The RST pin has a 20 kΩ pull-up resistor to VDD that can be
used to create a simple power-up reset circuit. A capacitor from
RST to ground holds RST low for some time while the rest of
the device stabilizes. The low condition causes all the outputs to
be disabled. The capacitor then charges through the pull-up
Rev. PrA | Page 24 of 32
resistor to the high state, thus allowing full programming
capability of the device.
Broadcast
The AD8176 logic interface has a broadcast mode, in which all
first rank latches can be simultaneously parallel-programmed to
the same data in one write-cycle. This is especially useful in
clearing random first rank data after power-up. To access the
broadcast mode, the part is parallel-programmed using the
device pins WE, A0 to A3, D0 to D4 and UPDATE. The only
difference is that the SER/PAR pin is held low, as if serial
programming were taking place. By holding CLK high, no serial
clocking will occur, and instead, the WE can be used to clock all
first rank latches in the chip at once.
Differential Input
Each differential input to the AD8176 is applied to a differential
receiver. These receivers allow the user to drive the inputs with
an uncertain common-mode voltage, such as from a remote
source over twisted pair. The receivers respond only to the
differences in input voltages and restore an internal common-
mode suitable for the internal signal path. Noise or crosstalk,
which affect each receiver’s inputs equally, are rejected by the
input stage, as specified by its common-mode rejection ratio
(CMRR).
Furthermore, the overall common-mode voltage of all three
differential pairs comprising an RGB channel is processed and
rejected by a separate circuit block. For example, a static
discharge or a resistive voltage drop in a middle-of-CAT5-run
with sync-on CM signaling coupling into all three pairs in an
RGB channel are rejected at the output of the AD8176, while
the sync-on CM signals are allowed through the switch.
The circuit configuration used by the differential input receivers
is similar to that of several Analog Devices general-purpose
differential amplifiers, such as the AD8131. The topology is that
of a voltage-feedback amplifier with internal gain resistors. The
input differential impedance for each receiver is 5 kΩ in parallel
with 10 kΩ or 3.33 kΩ, as shown in Figure 24.
IN+
IN–
R
G
R
G
R
CM
RCVR
R
F
R
F
OUT–
OUT+
TO SWITCH MATRIX
0
Figure 24. Input Receiver Equivalent Circuit
This impedance creates a small differential termination error if
the user does not account for the 3.33 kΩ parallel element.
However, this error is less than 1% in most cases. Additionally,
the source impedance driving the AD8176 appears in parallel
with the internal gain-setting resistors, such that there may be a
gain error for some values of source resistance. The AD8176 is
adjusted such that its gain is correct when driven by a back-
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD8176-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:475 MHz, Triple 16 】 9 Video Crosspoint Switch |
| AD8177 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8177ABPZ | 功能描述:IC VIDEO CROSSPOINT SWIT 676BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:- 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，FCBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8177-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8178 | 制造商:AD 制造商全稱:Analog Devices 功能描述:450 MHz, Triple 16 】 5 Video Crosspoint Switch |
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