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參數資料
| 型號： | AD8351ARM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Low Distortion Differential RF/IF Amplifier |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 465K |
| 代理商： | AD8351ARM-REEL7 |
REV. B
–12–
AD8351
SINGLE-
ENDED
50
SOURCE
R1
50
100nF
25
100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
VOCM
25
25
DIGITAL
OUT
AD6645
AIN
AIN
VREF
100nF
R
F
Figure 8. ADC Driving Application Using Single-Ended Input
ANALOG MULTIPLEXING
The AD8351 can be used as an analog multiplexer in applications
where it is desirable to select multiple high speed signals. The
isolation of each device when in a disabled state (PWUP pin pulled
low) is about 60 dBc for the maximum input level of 0.5 V p-p out
to 100 MHz. The low output noise spectral density allows for a
simple implementation as depicted in Figure 9. The PWUP inter-
face can be easily driven using most standard logic interfaces. By
using an N-bit digital interface, up to N devices can be controlled.
Output loading effects and noise need to be considered when using
a large number of input signal paths. Each disabled AD8351 pre-
sents approximately a 700
load in parallel with the 150
output
source impedance of the enabled device. As the load increases due
to the addition of N devices, the distortion performance will degrade
due to the heavier loading. Distortion better than –70 dBc can be
achieved with four devices muxed into a 1 k
load for signal fre-
quencies up to 70 MHz.
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT 1
OPLO
OPHI
BIT 1
PWUP
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT 2
OPLO
OPHI
BIT 2
PWUP
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT N
OPLO
OPHI
BIT N
PWUP
MUX
OUTPUT
LOAD
N-BIT
DIGITAL
INTERFACE
Figure 9. Using Several AD8351s to Form an
N-Channel Analog MUX
I/O CAPACITIVE LOADING
Input or output direct capacitive loading greater than a few pico-
farads can result in excessive peaking and/or oscillation outside
the pass band. This results from the package and bond wire induc-
tance resonating in parallel with the input/output capacitance of
the device and the associated coupling that results internally
through the ground inductance. For low resistive load or source
resistance, the effective Q is lower, and higher relative capaci-
tance termination(s) can be allowed before oscillation or excessive
peaking occurs. These effects can be eliminated by adding series
input resistors (R
IP
) for high source capacitance, or series output
resistors (R
OP
) for high load capacitance. Generally less than
25
is all that is required for I/O capacitive loading greater than
~2 pF. The higher the C, the smaller the R parasitic suppression
resistor required. In addition, R
IP
also helps to reduce low gain
in-band peaking, especially for light resistive loads.
AD8351
R
L
1k
C
STRAY
C
STRAY
R
IP
R
IP
R
G
R
OP
R
OP
C
L
C
L
Figure 10. Input and Output Parasitic Suppression
Resistors, R
IP
and R
OP
, Used to Suppress
Capacitive Loading Effects
Due to package parasitic capacitance on the R
G
ports, high R
G
values (low gain) cause high ac-peaking inside the pass band,
resulting in poor settling in the time domain. As an example,
when driving a 1 k
load, using 25
for R
IP
reduces the peaking
by ~7 dB for R
G
equal to 200
(A
V
= 10 dB) (see Figure 11).
Figure 11. Reducing Gain Peaking with Parasitic
Suppressing Resistors (R
IP
= 25
, R
L
= 1 k
)
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