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參數資料
| 型號： | AD8351ARM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Low Distortion Differential RF/IF Amplifier |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 465K |
| 代理商： | AD8351ARM-REEL7 |
REV. B
AD8351
–13–
It is important to ensure that all I/O, ground, and R
G
port traces
be kept as short as possible. In addition, it is required that the
ground plane be removed from under the package. Due to the
inverse relationship between the gain of the device and the value
of the R
G
resistor, any parasitic capacitance on the R
G
ports can
result in gain-peaking at high frequencies. Following the precau-
tions outlined in Figure 12 will help to reduce parasitic board
capacitance, thus extending the device’s bandwidth and reducing
potential peaking or oscillation.
COPLANAR
WAVEGUIDE
OR STRIP
2
1
3
4
5
9
10
8
7
6
R
T
R
IP
R
T
R
IP
R
G
R
OP
R
OP
Hi-Z
AGND
AGND
Figure 12. General Description of Recommended
Board Layout for High-Z Load Conditions
TRANSMISSION LINE EFFECTS
As noted, stray transmission line capacitance, in combination with
package parasitics, can potentially form a resonant circuit at high
frequencies, resulting in excessive gain peaking. R
F
transmission
lines connecting the input and output networks should be designed
such that stray capacitance is minimized. The output single-ended
source impedance of the AD8351 is dynamically set to a nominal
value of 75
. Therefore, for a matched load termination, the
characteristic impedance of the output transmission lines should be
designed to be 75
. In many situations, the final load impedance
may be relatively high, greater than 1 k
. It is suggested that the
board be designed as shown in Figure 12 for high impedance load
conditions. In most practical board designs, this requires that
the printed-circuit board traces be dimensioned to a small width
(~5 mils) and that the underlying and adjacent ground planes are
far enough away to minimize capacitance.
Typically the driving source impedance into the device will be
low and terminating resistors will be used to prevent input reflec-
tions. The transmission line should be designed to have the
appropriate characteristic impedance in the low-Z region. The
high impedance environment between the terminating resistors
and device input pins should not have ground planes under-
neath or near the signal traces. Small parasitic suppressing
resistors may be necessary at the device input pins to help desensitize
(“de-Q”) the resonant effects of the device bond wires and
surrounding parasitic board capacitance. Typically, 25
series
resistors (size 0402) adequately de-Q the input system without a
significant decrease in ac performance.
Figure 13 illustrates the value of adding input and output series
resistors to help desensitize the resonant effects of board parasitics.
Overshoot and undershoot can be significantly reduced with the
simple addition of R
IP
and R
OP
.
TIME (ns)
0
4
V
–0.5
–1.5
0
–1.0
1.5
0.5
1
3
1.0
2
R
IP
= R
OP
= 25
NO R
IP
OR R
OP
R
OP
= 25
Figure 13. Step Response Characteristics with and
without Input and Output Parasitic Suppression Resistors
CHARACTERIZATION SETUP
The test circuit used for 150
and 1 k
load testing is provided
in Figure 14. The evaluation board uses balun transformers to
simplify interfacing to single-ended test equipment. Balun effects
need to be removed from the measurements in order to accu-
rately characterize the performance of the device at frequencies
exceeding 1 GHz.
The output L-pad matching networks provide a broadband
impedance match with minimum insertion loss. The input
lines are terminated with 50
resistors for input impedance
matching. The power loss associated with these networks needs
to be accounted for when attempting to measure the gain of the
device. The required resistor values and the appropriate inser-
tion loss and correction factors used to assess the voltage gain
are provided in Table II.
Table II. Load Conditions Specified Differentially
Conversion
Factor
20 log (S21)
to 20 log (A
V
)
7.6 dB
25.9 dB
Total
Insertion
Loss
Load
Condition
150
1 k
R1
43.2
475
R2
86.6
52.3
5.8 dB
15.9 dB
BALANCED
SOURCE
R
S
50
0.1nF
0.1nF
100nF
R
LOAD
R
S
50
R
T
50
R
T
50
50 CABLE
50 CABLE
AD8351
DUT
R1
100nF
50 CABLE
50 CABLE
R1
R2
R2
50
50
50
TEST
EQUIPMENT
Figure 14. Test Circuit
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