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參數資料
| 型號： | AD8362ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數： | 18/36頁 |
| 文件大?。?/td> | 700K |
| 代理商： | AD8362ARU |
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AD8362
The most satisfactory way to quantify slew-rate limitations is by
considering the peak currents that can be generated by the
squaring cells. During a fast increase in input level, the peak
current into the integrating (loop filter) capacitance, CLPF, is
approximately 2.5 mA. The actual value depends on several
factors, including the size of the step, and extremes in chip
temperature. The voltage across the 1 nF capacitor thus
increases at a rate of nominally 2.5 V/μs. Because the output
buffer has a gain of 5, the output slew rate is 12.5 V/μs. The peak
rate persists up to a point about 10 dB below the final value,
after which the response gradually converges on the linear
system response, as noted previously.
Rev. B | Page 18 of 36
On the other hand, during a fast decrease in input level, the
peak current in CLPF in the opposite (discharging) direction is
much smaller; it is roughly 25 μA. Thus, the slew rate for VOUT
in the descending direction is only about 0.125 V/μs for CLPF =
1 nF. Discharging over the full 3 V range (a 60 dB reduction of
input) requires a time interval of ~24 μs. These figures are
verified in the results shown in Figure 44.
ALTERATION OF THE INTERNAL TARGET VOLTAGE
The AD8362 incorporates several features that extend its
versatility. One of these is the ability to alter the target
voltage. As noted, the output of the VGA is forced to a
value set by the internal bias voltage (V
ATG
= 0.06 × VTGT)
applied to the reference squaring cell. It is normally set to 75
mV dc by connecting VTGT to the 1.25 V reference voltage at
the VREF pin. However, it may optionally be varied from 0 V
up to ±0.24 V (±4 V at VTGT). Note that the sign of this input
is unimportant, because it is internally squared.
By lowering V
ATG
, the output of the VGA needed to balance the
output currents of the two matched squaring cells is similarly
lowered. This reduces the intercept in precisely the same ratio.
Thus, if we halve the setpoint target voltage by halving the
voltage applied to the VTGT pin, the intercept moves to the left
(to a smaller input level) by 6.02 dB. This effectively doubles the
measurement system’s sensitivity.
Furthermore, because the signal amplitude needed to drive the
squaring cell is halved, the output stage of the VGA now has
twice the dynamic headroom (before clipping) and can handle
waveforms having crest factors that are twice as large. Figure 45
shows the overall response for an illustrative set of values of
VTGT = 0.3 V, 0.533 V, 0.949 V, 1.687 V, and 3.0 V. While this is
usually a fixed dc voltage, it can also be a time-varying, unipolar
or bipolar voltage, in which case the overall operation is rather
more complex. For example, when VTGT is derived from
VOUT
,
the dynamic range can be extended to over 80 dB.
Examples of such uses of this feature are presented later.
RMS INPUT VOLTAGE (V)
R
100
μ
1m
10m
10
O
–10
–5
0
5
10
0.2
0.7
1.2
1.7
2.2
2.7
3.2
3.7
0.1
1
VTGT = 300mV
VTGT = 533mV
VTGT = 949mV
VTGT = 1.69V
VTGT = 3.0V
0
Figure 45. Response with VTGT Varied from 0.3 V to 3 V in 5 dB Steps,
Showing the Proportional Shift in Intercept
EFFECTS AT EACH END OF DYNAMIC RANGE
All AGC loops have a limited minimum and maximum input
beyond which the system cannot respond correctly. However,
the output of a well-behaved system is in error in such a way as
to avoid anomalous measurements. For an input below its
minimum capability, the output should not turn around to
falsely indicate a higher input value; for inputs above its
maximum capability, the output should not fold over and return
to some lower value.
The actual behavior of the AD8362 under these conditions can
be seen in the set of plots in Figure 45, the lower panel of which
shows the deviation from the ideal response with a slope of
50 mV/dB. For inputs below a certain level corresponding to the
point at which the VGA is operating at its maximum gain, its
output can no longer meet the rms amplitude target set by
VTGT, so the output moves quickly to its minimum value in an
attempt to provide the needed extra gain. As VTGT is altered,
the corresponding end-limit voltage moves to the left or to the
right.
On the other hand, when the input is above a certain upper
limit where the VGA gain has been driven to its minimum
gain, any further increase drives its output well above the target
voltage needed to balance the loop. The resulting integration of
this internal error signal causes VOUT to rise abruptly. In either
case, this output takes on a safe value and does not fold back
under any conditions.
The dynamic range, the “dB distance” between these limits, is
not basically dependent on VTGT. The middle line in the plots
of Figure 45 (VTGT = 0.949 V) extends from 0.5 mV to 1.5 V
between the ±1% error points; the dynamic range is thus
slightly over 68 dB. For other values of VTGT, this basic 68 dB
range just moves to the left or to the right.
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相關代理商/技術參數 |
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| AD8362ARU-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 Hz to 3.8 GHz 65 dB TruPwr? Detector |
| AD8362ARU-REEL7 | 功能描述:IC PWR DETECTOR 3.8GHZ 16-TSSOP RoHS:否 類別:RF/IF 和 RFID >> RF 檢測器 系列:- 產品變化通告:Product Discontinuation 15/May/2006 標準包裝:3,000 系列:- 頻率:100MHz ~ 2GHz RF 型:手機，GSM，DCS，PCS 輸入范圍:- 精確度:- 電源電壓:2.7 V ~ 5.5 V 電流 - 電源:300µA 包裝:帶卷 (TR) 封裝/外殼:SC-74，SOT-457 其它名稱:NCS5000SNT1GOS |
| AD8362ARUZ | 功能描述:IC PWR DETECTOR 3.8GHZ 16-TSSOP RoHS:是 類別:RF/IF 和 RFID >> RF 檢測器 系列:- 產品變化通告:Product Discontinuation 15/May/2006 標準包裝:3,000 系列:- 頻率:100MHz ~ 2GHz RF 型:手機，GSM，DCS，PCS 輸入范圍:- 精確度:- 電源電壓:2.7 V ~ 5.5 V 電流 - 電源:300µA 包裝:帶卷 (TR) 封裝/外殼:SC-74，SOT-457 其它名稱:NCS5000SNT1GOS |
| AD8362ARUZ | 制造商:Analog Devices 功能描述:RMS Detector IC |
| AD8362ARUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector |
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