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參數(shù)資料
型號: AD8362ARU
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調(diào)理
英文描述: 50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封裝: MO-153AB, TSSOP-16
文件頁數(shù): 31/36頁
文件大小: 700K
代理商: AD8362ARU
AD8362
Table 5. Suggested Values for Use in Scheme of Figure 63
R1 ()
R2 ()
V
SLP
' (V/decade)
O/C
S/C
0.868
1904
96
0.870
1346
654
0.890
872
1128
0.914
480
1520
0.942
200
1800
0.972
HIGH SLOPE DETECTORS CENTERED ON A
NARROW WINDOW
The situation often arises in system monitoring in which an
input signal varies by much less than 60 dB, and the highest
possible sensitivity and accuracy of measurement is required
within a narrow window of input magnitudes. Adapting the
AD8362 to this task requires that the slope be increased and the
intercept repositioned. Using an attenuator from VOUT to
VSET, any slope >50 mV/dB can be realized. Then, using a
fraction of VREF (or external reference voltage), the particular
region of the dynamic range to be measured can be positioned
wherever desired. In these high slope applications, the full rail-
to-rail output swing of the AD8362 can be exploited.
Rev. B | Page 31 of 36
V
Z
' (mV)
0.334
0.336
0.333
0.340
0.355
0.380
K
C
(m)
11.3
10.4
6.5
3.7
1.5
0.5
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
AD8362
V
OUT
R2
R1
INTERCEPT OFFSET
VOLTAGE, V
SHIFT
SLOPE
(V/dec)
2
4
5
10
R1
(k
)
4.02
8.66
8.66
9.1
R2
(k
)
4.32
3.01
2.15
1.02
0
Figure 65. Slope and Intercept Adjustment
Figure 65 shows the basic connections for this mode of use; the
intercept repositioning voltage V
SHIFT
can be introduced by
adding a third resistor from VREF to VSET with recalculated
values of R1 and R2 or by using an external voltage source.
Figure 66 presents the simulation results for a log slope of
100 mV/dB (2 V/dec) covering two-decade spans over several
sub-ranges, while Figure 67 shows the results for a slope of
200 mV/dB (4 V/dec), providing just a one-decade span.
To accurately reposition the range (intercept) when very high
slopes are used, a low output impedance DAC can be used to
provide V
SHIFT
. Figure 68 shows simulated results for a slope of
500 mV/dB (10 V/dec) presuming this configuration. In all
cases, the fixed-pattern ripple in the log conformance remains
unchanged in dB terms. Residual fluctuations due to insufficient
averaging (in low frequency applications) are likewise
unaffected in their equivalent decibel value, though greater in
absolute voltage terms.
RMS INPUT VOLTAGE (V)
S
100
μ
1m
10m
10
O
–30
0
10
30
0
1
3
4
0.1
1
2
20
–20
–10
0
Figure 66. Illustrative Results for Slope of 100 mV/dB
RMS INPUT VOLTAGE (V)
S
100
μ
1m
10m
10
O
–30
0
10
30
0
1
3
4
0.1
1
2
20
–20
–10
0
Figure 67. Illustrative Results for Slope of 200 mV/dB
RMS INPUT VOLTAGE (V)
S
100
μ
1m
10m
10
O
–30
0
10
30
0
1
3
4
0.1
1
2
20
–20
–10
0
Figure 68. Illustrative Results for Slope of 10 mV/dec
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