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參數資料
| 型號： | AD8362ARUZ-REEL71 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector |
| 中文描述： | 50赫茲到2.7 GHz 60分貝TruPwr⑩探測器 |
| 文件頁數： | 15/36頁 |
| 文件大小： | 700K |
| 代理商： | AD8362ARUZ-REEL71 |
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AD8362
CIRCUIT DESCRIPTION
The AD8362 is a fully calibrated, high accuracy, rms-to-dc
converter providing a measurement range of over 60 dB. It is
capable of operation from signals as low in frequency as a few
Hertz to at least 2.7 GHz. Unlike earlier rms-to-dc converters,
the response bandwidth is completely independent of the signal
magnitude. The 3 dB point occurs at about 3.5 GHz. The
capacity of this part to accurately measure waveforms having a
high peak-to-rms ratio (crest factor) is independent of either
the signal frequency or its absolute magnitude, over a wide
range of conditions.
Rev. B | Page 15 of 36
This unique combination allows the AD8362 be to used with
equal ease as a calibrated RF wattmeter covering a power ratio
of >1,000,000:1, as a power controller in closed-loop systems, or
as a general-purpose rms-responding voltmeter, and in many
other low frequency applications.
VGA
BAND GAP
REFERENCE
INHI
INLO
CHPF
SETPOINT
INTERFACE
OFFSET
NULLING
VSET
V
SET
VREF
V
REF
1.25V
×
0.06
V
TGT
ACOM
VTGT
X
2
X
2
V
SIG
V
ATG
OUTPUT
FILTER
C
F
CLPF
C
EXTERNAL
INTERNAL RESISTORS
SET BUFFER GAIN TO 5
V
OUT
VOUT
ACOM
I
SQU
I
TGT
–25dB TO +43dB
MATCH WIDE-
BAND SQUARERS
AMPLITUDE TARGET
FOR V
SIG
G
SET
0
Figure 42. Basic Structure of the AD8362
The part comprises the core elements of a high performance
AGC loop (Figure 42), laser-trimmed during manufacture to
close tolerances while fully operational at a test frequency of
100 MHz. Its linear, wideband, variable gain amplifier (VGA)
provides a general voltage gain, G
SET
; this may be controlled in a
precisely exponential (linear-in-dB) manner over the full 68 dB
range from 25 dB to +43 dB by a voltage V
SET
. However, to
provide adequate guard-banding, only the central 60 dB of this
range, from 21 dB to +39 dB, is normally used. Later, it is
shown how this basic range may be shifted either up or down,
and even extended to >80 dB. The VGA gain has the form
(
GNS
O
SET
V
VSET
G
G
=
exp
)
(1)
where
G
O
is a basic fixed gain and
V
GNS
is a scaling voltage that
defines the gain slope (the dB change per volt). Note that the
gain decreases with V
SET
. The VGA output is
(
)
GNS
IN
O
IN
SET
SIG
V
VSET
V
G
V
G
V
exp
=
=
(2)
where
V
IN
is the ac voltage applied to the input terminals
of the AD8362.
As is later explained more fully, the input drive may be
either single-sided or differential but optimum performance at
input drive. The effect of HF imbalances when using a single-
sided drive is less apparent at low frequencies (from 50 Hz
to 500 MHz), but the peak input voltage capacity is always
halved relative to differential operation (see the Using the
AD8362 section).
SQUARE-LAW DETECTION
The output of the variable-gain amplifier, V
SIG
, is
applied to a wideband square law detector, which provides a
true rms response to this alternating signal that is essentially
independent of waveform up to crest factors of 6. Its output
is a fluctuating current, I
SQU
, having a positive mean value. This
current is integrated by an on-chip capacitance, C
F
; this is
usually augmented by an external capacitance, CLPF, to extend
the averaging time. The resulting voltage is buffered by a gain-
of-5, dc-coupled amplifier whose rail-to-rail output, VOUT, may
be used either for measurement or control purposes.
In most applications, the AGC loop is closed via the setpoint
interface pin, VSET, to which the VGA gain-control voltage
VSET is applied. In measurement modes, the closure is direct
and local by a simple connection from the output the VOUT
pin to the VSET pin. In controller modes, the feedback path is
around some larger system, but the operation is the same.
The fluctuating current, I
SQU
, is balanced against a fixed setpoint
target current, I
TGT
, using current mode subtraction. With the
exact integration provided by the capacitor(s), the AGC loop
equilibrates when
(
TGT
SQU
I
I
MEAN
=
)
(3)
The current
I
TGT
is provided by a second-reference squaring
cell whose input is the amplitude-target voltage V
ATG
. This is a
fraction of the voltage VTGT applied to a special interface that
accepts this input at the VTGT pin. Since the two squaring cells
are electrically identical and are carefully implemented in the
IC, process and temperature-dependent variations in the
detailed behavior of the two square-law functions cancel.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD8362-EVAL | 制造商:Analog Devices 功能描述:RF DETECTOR, 50 HZ TO 2.7GHZ 60 DB TRUPWR DETECTOR - Bulk |
| AD8362-EVALZ | 功能描述:BOARD EVAL FOR AD8362 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發套件，板 系列:TruePower™ 標準包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關產品:- 已供物品:模塊 其它名稱:SER3796 |
| AD8363 | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 Hz to 6 GHz, 50 dB TruPwr? Detector |
| AD8363_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 Hz to 6 GHz, 50 dB TruPwr? Detector |
| AD8363ACPZ-R2 | 制造商:Analog Devices 功能描述:TRUE RMS PWR DETECTOR 24LFCSP EP - Tape and Reel |
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