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參數資料
| 型號： | AD8362ARUZ-REEL71 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector |
| 中文描述： | 50赫茲到2.7 GHz 60分貝TruPwr⑩探測器 |
| 文件頁數： | 16/36頁 |
| 文件大小： | 700K |
| 代理商： | AD8362ARUZ-REEL71 |
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AD8362
Accordingly, VTGT (and its fractional part V
ATG
) determines the
output that must be provided by the VGA for the AGC loop to
settle. Since the scaling parameters of the two squarers are
accurately matched, it follows that Equation 3 is satisfied only
when
(
)
ATG
SIG
V
V
MEAN
=
Rev. B | Page 16 of 36
2
2
(4)
In a formal solution, one would then extract the square root of
both sides to provide an explicit value for the root-mean-square
(rms) value. However, it is apparent that by forcing this identity,
through varying the VGA gain and extracting the mean value
by the filter provided by the capacitor(s), the system inherently
establishes the relationship
(
)
ATG
SIG
V
V
rms
=
(5)
Substituting the value of V
SIG
from Equation 2, we have
(
IN
O
VSET
V
G
rms
exp
)
[
]
ATG
GNS
V
V
=
(6)
As a measurement device, V
IN
is the unknown quantity and all
other parameters can be fixed by design. Solving Equation 6:
[
ATG
IN
O
VSET
V
V
G
rms
exp
=
]
(
)
GNS
V
(7)
so
(
)
[
]
Z
IN
GNS
V
V
rms
V
VSET
log
=
(8)
The quantity
V
Z
=
V
ATG
/
G
O
is defined as the intercept voltage
because
VSET
must be 0 when
rms
(
V
IN
) =
V
Z
.
When connected as a measurement device, the output of the
buffer is tied directly to VSET, which closes the AGC loop.
Making the substitution
VOUT
=
VSET
and changing the log
base to 10, as needed in a decibel conversion, we have
(
SLP
V
rms
V
VOUT
10
log
=
)
[
]
Z
IN
V
(9)
where
V
SLP
is the slope voltage, that is, the change in output
voltage for each decade of change in the input amplitude.
(Note that
V
SLP
=
V
GNS
log (10) = 2.303
V
GNS
). In the AD8362,
V
SLP
is laser trimmed to 1 V using a 100 MHz test signal.
Because a decade corresponds to 20 dB, this slope may also be
stated as 50 mV/dB. It is later shown how the effective value of
V
SLP
may be altered by the user.
Likewise, the intercept
V
Z
is also laser trimmed to 316 μV
(70 dBV). In an ideal system,
VOUT
would cross zero for an
rms input of that value. In a single-supply realization of the
function,
VOUT
cannot run fully down to ground; here,
V
Z
is
the extrapolated value. In measurement modes, the output
ranges from 0.5 V for
V
IN
= 1 mV (input values are stated as
rms, outputs values as dc), up to a voltage 60 dB × 50 mV/dB =
3 V above this for
V
IN
= 1 V, that is, to 3.5 V. Figure 43 shows the
ideal form of Equation 9 scaled as in the AD8362.
RMS INPUT VOLTAGE (100
μ
V TO 3.2V)
10
μ
V
O
1mV
10mV
100mV
1V
10V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
Figure 43. Ideal Response of the AD8362
EFFECT OF INPUT COUPLING ON THE INTERCEPT
VALUE
Reductions of V
IN
due to coupling losses directly affect V
Z
. In
high frequency applications, several factors contribute to the
coupling of the source into the IC, including the board and
package resonances and attenuation. Any uncertainties in the
input impedance result in the intercept expressed in power
terms, which is nominally 57 dBm for a 50 system, being
less accurately determined than when stated in dBV (that is, in
pure voltage) terms. On the other hand, the slope V
SLP
is
unaffected by all such impedance or coupling uncertainties.
OFFSET ELIMINATION
To address the small dc offsets that arise in the variable gain
amplifier, an offset-nulling loop is used. The high-pass corner
frequency of this loop is internally preset to 1 MHz, sufficiently
low for most HF applications. When using the AD8362 in LF
applications, the corner frequency can be reduced as needed by
the addition of a capacitor from the CHPF pin to ground having
a nominal value of 200 μF/Hz. For example, to lower the high-
pass corner frequency to 150 Hz, a capacitance of 1.33 μF is
required. The offset voltage varies depending on the actual gain
at which the VGA is operating, and thus, on the input signal
amplitude.
Baseline variations of this sort are a common aspect of all
VGAs, although more evident in the AD8362 because of the
method of its implementation, which causes the offsets to
ripple along the gain axis with a period of 6.33 dB. When an
excessively large value of CHPF is used, the offset correction
process may lag the more rapid changes in the VGA’s gain,
which may increase the time required for the loop to fully settle
for a given steady input amplitude.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD8362-EVAL | 制造商:Analog Devices 功能描述:RF DETECTOR, 50 HZ TO 2.7GHZ 60 DB TRUPWR DETECTOR - Bulk |
| AD8362-EVALZ | 功能描述:BOARD EVAL FOR AD8362 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發套件，板 系列:TruePower™ 標準包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關產品:- 已供物品:模塊 其它名稱:SER3796 |
| AD8363 | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 Hz to 6 GHz, 50 dB TruPwr? Detector |
| AD8363_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 Hz to 6 GHz, 50 dB TruPwr? Detector |
| AD8363ACPZ-R2 | 制造商:Analog Devices 功能描述:TRUE RMS PWR DETECTOR 24LFCSP EP - Tape and Reel |
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