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參數(shù)資料
| 型號： | AD8369 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | 45 dB Digitally Controlled VGA LF to 600 MHz |
| 中文描述： | 45分貝的數(shù)字控制VGA低頻至600兆赫 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 968K |
| 代理商： | AD8369 |
REV. 0
AD8369
–13–
Gm CELLS
GAIN STEP SELECTION
DIGITAL
3dB SWITCHED
ATTENUATOR
BIAS
FIXED
GAIN
INLO
CMDC
INHI
20pF
22pF
OPLO
OPHI
V
S
V
S
V
S
/2
V
S
/2
100
100
~V
2– 0.7
Figure 1. General Block Diagram, Control and Signal Paths Are Differential
THEORY OF OPERATION
The AD8369 is a digitally controlled fully differential VGA
based on a variation of Analog Devices’ patented X-AMP archi-
tecture (Figure 1). It provides accurate gain control over a 45 dB
span with a constant –3 dB bandwidth of 600 MHz.
The 3 dB gain steps can be controlled by a user-selectable
parallel- or serial-mode digital interface. A single pin (SENB)
selects the mode. The AD8369 is designed for optimal
operation when used in a fully differential system, although
single-ended operation is also possible. Its nominal input and
output impedances are 200
W
.
Input Attenuator and Output 3 dB Step
The AD8369 is comprised of a seven-stage R-2R ladder net-
work (eight taps) and a selected Gm stage followed by a
fixed-gain differential amplifier. The ladder provides a total
attenuation of 42 dB in 6 dB steps. The full signal is applied to
the
amplifier using the first tap; at the second tap, the signal
is 6 dB lower and so on. A further 3 dB interpolating gain step is
introduced at the output of the fixed gain amplifier, providing
the full 45 dB of gain span.
Fixed Gain Amplifier
The fixed gain amplifier is driven by the tap point of the R-2R
ladder network via the selected Gm cell. The output stage is a
complementary pair of current sources, loaded with internal
100
W
resistors to ac ground which provides a 200
W
differential
output impedance. The low frequency gain of the AD8369
can be approximated by the equation:
ê
200
V
V
IN
OUT
L
R
L
n
R
=
+
ˉ
ê
á
ˉ
-
(
)
0 6
.
200
1
2
15
where
R
L
is the external load resistor in ohms and
n
is the gain
code; 0 is the minimum gain code and 15 is the maximum gain
code. The external load, which is in parallel combination with
the internal 200
W
output resistor, affects the overall gain and
peak output swing.
Note that the external load has no effect on the
gain step size.
Input and Output Interfaces
The dc working points of the differential input and output inter-
faces of the AD8369 are internally biased. The inputs INHI and
INLO are biased to a diode drop below V
S
/2 (~1.7 V for a 5 V
positive supply) to meet isolation and headroom constraints,
while the outputs OPHI and OPLO are centered on the supply
midpoint, V
S
/2, to provide the maximum output swing.
The internal V
S
/2 reference and the CMDC reference are buff-
ered and decoupled to ground via internal capacitors. The
input bias voltage, derived from this V
S
/2 reference, is brought
FREQUENCY – kHz
100
10
P
100
1000
90
80
70
60
50
40
30
20
10
0
10000
TPC 37. Power Supply Rejection Ratio, V
S
= 5 V,
R
L
= 1 k
W
, Maximum Gain
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|---|---|
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