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參數(shù)資料
| 型號(hào)： | AD8369 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 45 dB Digitally Controlled VGA LF to 600 MHz |
| 中文描述： | 45分貝的數(shù)字控制VGA低頻至600兆赫 |
| 文件頁(yè)數(shù)： | 2/24頁(yè) |
| 文件大小： | 968K |
| 代理商： | AD8369 |
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REV. 0
–2–
AD8369–SPECIFICATIONS
(V
= 5 V, T = 25 C, R
= 200 , R
L
= 1000 , Frequency = 70 MHz, at maximum gain,
unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
3 dB Bandwidth
LF
*
600
MHz
GAIN CONTROL INTERFACE
Voltage Gain Span
Maximum Gain
Minimum Gain
Gain Step Size
Gain Step Accuracy
Gain Step Response Time
45
40
–5
3
±
0.05
30
dB
dB
dB
dB
dB
ns
All bits high (1 1 1 1)
All bits low (0 0 0 0)
Over entire gain range, with respect to 3 dB step
Step = 3 dB, settling to 10% of final value
INPUT STAGE
Input Resistance
From INHI to INLO
From INHI to COMM, from INLO to COMM
From INHI to INLO
From INHI to COMM, from INLO to COMM
200
100
0.1
1.1
2
1.7
2.2
W
W
pF
pF
nV/
÷
Hz
V
V
Input Capacitance
Input Noise Spectral Density
Input Common-Mode DC Voltage Measured at pin CMDC
Maximum Linear Input
|V
INHI
– V
INLO
| at Minimum Gain
OUTPUT STAGE
Output Resistance
From OPHI to OPLO
From OPHI to COMM, from OPLO to COMM
From OPHI to OPLO
From OPHI to COMM, from OPLO to COMM
No input signal
Output step = 1 V
200
100
0.25
1.5
V
S
/2
1200
W
W
pF
pF
V
V/
m
s
Output Capacitance
Common-Mode DC Voltage
Slew Rate
POWER INTERFACE
Supply Voltage
Quiescent Current
vs. Temperature
Disable Current
vs. Temperature
3.0
5.5
42
52
750
1
V
mA
mA
m
A
mA
PWUP high
–40
∞
C
￡
T
A
￡
85
∞
C
PWUP low
–40
∞
C
￡
T
A
￡
85
∞
C
Pin PWUP
37
400
POWER UP INTERFACE
Enable Threshold
Disable Threshold
Response Time
1.0
V
V
m
s
2.2
Time delay following low to high transition
on PWUP until output settles to within 10%
of final value
PWUP = 5 V
7
Input Bias Current
160
m
A
DIGITAL INTERFACE
Pins SENB, BIT0, BIT1, BIT2, BIT3,
and DENB
Low Condition
High Condition
Input Bias Current
2.0
V
V
m
A
3.0
Low input
150
Frequency = 10 MHz
Voltage Gain
Gain Flatness
Noise Figure
Output IP3
40.5
+0.05
*
7.0
+22
+22
dB
dB
dB
dBV rms
dBm
Within
±
10 MHz of 10 MHz
f1 = 9.945 MHz, f2 = 10.550 MHz
IMD
3
f1 = 9.945 MHz, f2 = 10.550 MHz
V
OPHI
– V
OPLO
= 1 V p-p composite
Second-Order, V
OPHI
– V
OPLO
= 1 V p-p
Third-Order, V
OPHI
– V
OPLO
= 1 V p-p
For
±
1 dB deviation from linear gain
–74
–72
–71
+3
+3
dBc
dBc
dBc
dBV rms
dBm
Harmonic Distortion
P1dB
*
The low frequency high-pass corner is determined by the capacitor on pin FILT, C
FILT
. See the Theory of Operation section for details.
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