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參數資料
型號: AD9211BCPZ-250
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter
中文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56
封裝: 8 X 8 MM, ROHS COMPLIANT, MO-220VLLD-2, LFCSP-56
文件頁數: 15/21頁
文件大小: 310K
代理商: AD9211BCPZ-250
Preliminary Technical Data
AD9211
Rev. PrA | Page 15 of 21
Figure 10. Single-Ended Input Configuration using SPI enabled CML function
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9211 the sample clock inputs
(CLK+ and CLK-) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK- pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias (See Figure X).
1.2V
CLK+
CLK-
2pF
2pF
AVDD
Figure .Equivalent Clock Input Circuit
Figure X shows one preferred method for clocking the AD9211.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD9211 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9211 while preserving the
fast rise and fall times of the signal, which are critical to a low
jitter performance.
Clock
Source
CLK+
CLK-
AD9230
Figure X. Transformer Coupled Differential Clock for AD9230/AD9211
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure X. The AD9512 (or same family) from offers excellent
jitter performance.
CLK+
CLK-
AD9230
0.1uF
0.1uF
AD9512
PECL
150
Ω
150
Ω
Figure X. Differential PECL Sample Clock for AD9230/AD9211
1.25Vp-p
R
4
9
.
9
Ω
0
.
1
μ
F
1
0
μ
F
0.1uF
A
D9211
VIN-
CML
VIN+
AVDD
AGND
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相關代理商/技術參數
參數描述
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