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參數資料
| 型號： | AD9211BCPZ-250 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56 |
| 封裝： | 8 X 8 MM, ROHS COMPLIANT, MO-220VLLD-2, LFCSP-56 |
| 文件頁數： | 16/21頁 |
| 文件大小： | 310K |
| 代理商： | AD9211BCPZ-250 |
AD9211
Preliminary Technical Data
Clock Input Considerations
Rev. PrA | Page 16 of 21
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance
characteristics. The AD9211 contains a DCS (duty cycle
stabilizer) that retimes the non-sampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows
a wide range of clock input duty cycles without affecting the
performance of the AD9211. Noise and distortion performance
are nearly flat for a wide range duty cycles with the DCS on.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the non-sampling edge. As a result, any changes to the
sampling frequency require approximately TBD clock cycles to
allow the DLL to acquire and lock to the new rate.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (f
INPUT
) due only to aperture jitter (t
J
) can be
calculated by
×
π
2
=
J
INPUT
t
f
20
log
SNR
In the equation, the rms aperture jitter represents the root-
mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
under-sampling applications are particularly sensitive to jitter,
see Figure 11.
INPUT FREQUENCY (MHz)
1
40
75
70
65
60
55
50
45
1000
100
10
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
S
Figure 11. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9211. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
POWER DISSIPATION AND POWER DOWN MODE
As shown in Figure 12 and Figure 14, the power dissipated by
the AD9211 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
Figure 12. AD9211-170, Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz
Figure 13. AD9211-200, Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz
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