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參數資料
型號: AD9228-65EB
廠商: Analog Devices, Inc.
英文描述: Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述: 四,12位,六十五分之四十○MSPS的串行LVDS 1.8弗吉尼亞州/ D轉換器
文件頁數: 1/52頁
文件大小: 1659K
代理商: AD9228-65EB
Quad, 12-bit, 40/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9228
FEATURES
Four ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power reduced signal option, IEEE 1596.3 similar
Data and frame clock outputs
315 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
www.analog.com
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
FUNCTIONAL BLOCK DIAGRAM
SERIAL
LVDS
REF
SELECT
+
AD9228
AGND
VIN–A
VIN+A
VIN–B
VIN+B
VIN–D
VIN+D
VIN–C
VIN+C
SENSE
VREF
AVDD
DRVDD
12
12
12
12
PDWN
REFT
REFB
D–A
D–B
D+B
D–D
D+D
D–C
D+C
FCO–
FCO+
DCO+
DCO–
CLK+
DRGND
CLK–
SERIAL PORT
INTERFACE
CSB
SCLK/DTP
SDIO/ODM
RBIAS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
PIPELINE
ADC
PIPELINE
ADC
PIPELINE
ADC
PIPELINE
ADC
DATA RATE
MULTIPLIER
0.5V
0
Figure 1.
capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9228 is available in a Pb-free, 48-lead LFCSP package. It is
specified over the industrial temperature range of 40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
Small Footprint. Four ADCs are contained in a small, space-
saving package; low power of 119 mW/channel at 65 MSPS.
2.
Ease of Use. A data clock output (DCO) is provided that
operates up to 390 MHz and supports double data rate
operation (DDR).
3.
User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
4.
Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
相關PDF資料
PDF描述
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