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參數(shù)資料
| 型號： | AD9228-65EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 四，12位，六十五分之四十○MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 1659K |
| 代理商： | AD9228-65EB |
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AD9228
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9228 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Rev. 0 | Page 21 of 52
Figure 50 shows one preferred method for clocking the AD9228.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9228 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9228 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
0.1μF
0.1μF
0.1μF
0.1μF
SCHOTTKY
DIODES:
HSM2812
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9228
MIN-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
0
Figure 50. Transformer Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 51. The
AD9510
/
AD9511
/
AD9512
/
AD9513
/
AD9514
/
AD9515
family of clock drivers offers excellent jitter performance.
INPUT
100
0.1μF
0.1μF
0.1μF
0.1μF
240
240
INPUT
0
AD9510/1/2/3/4/5
CLK
50
*
50
*
CLK
*50
RESISTORS ARE OPTIONAL
CLK–
CLK+
ADC
AD9228
Figure 51. Differential PECL Sample Clock
0
INPUT
100
0.1μF
0.1μF
0.1μF
0.1μF
50
*
INPUT
AD9510/1/2/3/4/5
CLK
50
*
CLK
*50
RESISTORS ARE OPTIONAL
Figure 52. Differential LVDS Sample Clock
CLK–
CLK+
ADC
AD9228
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 53). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0
INPUT
0.1μF
0.1μF
0.1μF
39
k
CMOS DRIVER
50
*
OPTIONAL
100
0.1μF
CLK
CLK
*50
RESISTOR IS OPTIONAL
Figure 53. Single-Ended 1.8 V CMOS Sample Clock
CLK–
CLK+
ADC
AD9228
0
INPUT
0.1μF
0.1μF
0.1μF
CMOS DRIVER
50
*
OPTIONAL
CLK
CLK
*50
RESISTOR IS OPTIONAL
0.1μF
CLK–
CLK+
ADC
AD9228
Figure 54. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9228 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9228. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. The DCS
function cannot be turned off.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 10 clock cycles
to allow the DLL to acquire and lock to the new rate.
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