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參數資料
型號: AD9228
廠商: Analog Devices, Inc.
英文描述: Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述: 四,12位,六十五分之四十○MSPS的串行LVDS 1.8弗吉尼亞州/ D轉換器
文件頁數: 25/52頁
文件大小: 1659K
代理商: AD9228
AD9228
Two output clocks are provided to assist in capturing data from
the AD9228. The DCO is used to clock the output data and is
equal to six times the sampling clock (CLK) rate. Data is
clocked out of the AD9228 and must be captured on the rising
and falling edges of the DCO that supports double data rate
Table 9. Flex Output Test Modes
Rev. 0 | Page 25 of 52
(DDR) capturing. The frame clock out (FCO) is used to signal
the start of a new output byte and is equal to the sampling clock
rate. See the timing diagram shown in Figure 2 for more
information.
Output Test
Mode Bit
Sequence
0000
0001
Pattern Name
OFF (default)
Midscale Short
Digital Output Word 1
N/A
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
N/A
N/A
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
Register 0x19 to Register 0x1A
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0000 1111 (8-bit)
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1010 0011 (8-bit)
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
Digital Output Word 2
N/A
Same
Subject
to Data
Format
Select
N/A
Yes
0010
+Full-Scale Short
Same
Yes
0011
Full-Scale Short
Same
Yes
0100
Checker Board
0101 0101 (8-bit)
01 0101 0101 (10-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
N/A
N/A
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
Register 0x1B to Register 0x1C
N/A
No
0101
0110
0111
PN Sequence Long
1
PN Sequence Short
1
One/Zero Word Toggle
Yes
Yes
No
1000
1001
User Input
One/Zero Bit Toggle
No
No
1010
1× Sync
N/A
No
1011
One Bit High
N/A
No
1100
Mixed Frequency
N/A
No
1
PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is
9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1
(short), defines the pseudorandom sequence.
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相關代理商/技術參數
參數描述
AD9228_07 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
AD9228-65EB 制造商:Analog Devices 功能描述:
AD9228-65EB1 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit
AD9228-65EBZ 功能描述:BOARD EVAL FOR AD9228 RoHS:是 類別:編程器,開發系統 >> 評估板 - 模數轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數量:1 位數:12 采樣率(每秒):94.4k 數據接口:USB 輸入范圍:±VREF/2 在以下條件下的電源(標準):- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板,軟件
AD9228ABCPZ-40 功能描述:IC ADC 12BIT SPI/SRL 40M 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率(每秒):20M 數據接口:并聯 轉換器數目:2 功率耗散(最大):155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP(7x7) 包裝:Digi-Reel® 輸入數目和類型:4 個單端,單極;2 個差分,單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
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